JPH05129555A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To constrict the margin of word line selecting voltage and to decrease the absolute value thereof by substantially matching the absolute value and the characteristic variation of the threshold voltage of sense MOSFET with those of an address selecting MOSFET constituting a memory cell. CONSTITUTION:A ward line selecting voltage generating circuit VCHG includes p-channel (second conductivity type) MOSFET Q4(second MOSFET) and an N-channel MOSFET Q12 (third MOSFET) interposed between the source of a sense MOSFET Q5 formed in the region of a memory array MARY and the ground potential. of the circuit. The gates of these MOSFETs are fed with a common internal power supply voltage VCL and the commonly connected drains thereof are coupled with the input terminal of a CMOS inverter N1. According to the constitution, absolute threshold voltage of the sense MOSFET and characteristic variation thereof can be substantially matched with those of an address selecting MOSFET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM (random access memory) adopting a static word line selection system.
The present invention relates to a technology that is particularly effective when used for such purposes.

[0002]

2. Description of the Related Art There is a static word line selection system in which a specified word line of a memory array is selectively placed in a selected state by selectively transmitting a predetermined word line selection voltage. There is a dynamic RAM that can be used.

A dynamic RAM adopting a static word line selection system is disclosed in, for example, Japanese Patent Application No. 1-65.
841 and the like.

[0004]

In a dynamic RAM or the like which adopts the static word line selection system, the potential of the word line selection voltage constitutes at least a memory cell from the internal power supply voltage supplied to the memory array and its peripheral circuits. It must be higher than the threshold voltage of the address selection MOSFET. In the conventional dynamic RAM or the like as described above, the word line selection voltage generation circuit that forms the word line selection voltage is arranged as a peripheral circuit outside the area of the memory array, and the potential of the word line selection voltage is For example, it is set based on the threshold voltages of a predetermined number of sense MOSFETs in series. As is well known, an extremely highly integrated memory array and a peripheral circuit including a relatively large number of random logics have different manufacturing processes and different substrate back bypass voltage potentials applied to respective regions. Therefore, the absolute value of threshold voltage and the change in characteristics are different between the address selection MOSFET formed in the area of the memory array and the sense MOSFET formed in the area of the peripheral circuit, resulting in the potential of the word line selection voltage. Increase the margin,
It becomes necessary to set the central value higher. As a result, the charge or discharge current increases as the level of the word line or the like changes, and the reduction in power consumption of the dynamic RAM or the like adopting the static word line selection method is hindered.

An object of the present invention is to compress a potential margin of a word line selection voltage in a dynamic RAM adopting a static word line selection system and reduce its absolute value. Another object of the present invention is to promote low power consumption of a dynamic RAM adopting a static word line selection system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a word line selection voltage generating circuit such as a dynamic RAM adopting a static word line selection system is provided with, for example, an N-channel type sense MOSFET that receives the word line selection voltage at its drain and gate.
And a pair of P-channel and N-channel MOSFETs that are provided in series between the source of the sense MOSFET and the ground potential of the circuit and commonly receive a predetermined internal power supply voltage at their gates, and these P-channel and N-channel MOSFETs. A CMOS inverter receiving the commonly-coupled drain potential of the CMOS inverter, and a level detection circuit using the output signal of the CMOS inverter as its output signal, and selectively replenishing the potential of the word line selection voltage according to the output signal of the level detection circuit. A voltage generating circuit is used to form the sense MOSFET under the same conditions as the address selection MOSFETs forming the memory cell and in the memory array region.

[0008]

According to the above means, the absolute value of the threshold voltage of the sense MOSFET and its characteristic change can be made substantially coincident with the address selection MOSFET forming the memory cell. The potential margin can be compressed and its absolute value can be reduced. As a result, it is possible to reduce the charge or discharge current associated with the level change of the word line or the like, and promote the low power consumption of the dynamic RAM or the like adopting the static word line selection method.

[0009]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. 2 and 3 and 4, the memory array MARY and the word line drive circuit WD and the word line selection voltage generation circuit VC included in the dynamic RAM of FIG. 1 are shown.
The circuit diagrams of one embodiment of the HG are shown respectively. Based on these drawings, an outline of the structure and operation of the dynamic RAM of this embodiment and its features will be described.
The circuit elements of FIGS. 2 to 4 and the circuit elements constituting each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In addition, in FIGS. 2 to 4, a MOSFET whose channel (back gate) part is provided with an arrow
(Metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor) is a P-channel type and is shown separately from an N-channel MOSFET without an arrow. ..

In FIG. 1, the basic structure of the dynamic RAM of this embodiment is a memory array MARY which occupies most of the semiconductor substrate surface. As shown in FIG. 2, the memory array MARY has m + 1 word lines W0 to Wm arranged in parallel in the vertical direction of FIG.
And n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction (here, for example, non-inverted bit line B
0 and the inversion bit line B0B together, the complementary bit line B0
It is expressed by adding * like *. Also, so-called inverted signals or inverted signal lines that are selectively brought to a low level when they are validated are indicated by adding B to the end of their names. The same shall apply hereinafter) and. At the intersection of these word lines and complementary bit lines, there are (m + 1) × information storage capacitors Cs and address selection MOSFETs Qa.
(N + 1) dynamic memory cells are arranged in a grid pattern. Address selection MOSFETQ of n + 1 memory cells arranged in the same row of the memory array MARY
The gates of a are commonly connected to the corresponding word lines W0 to Wm. Further, the drains of the address selection MOSFETs Qa of the m + 1 memory cells arranged in the same column are alternately coupled to the corresponding non-inverted or inverted signal lines of the complementary bit lines B0 * to Bn * with a predetermined regularity. .. A predetermined plate voltage HV is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells forming the memory array MARY.

In this embodiment, the memory array MAR
Y further includes one sense MOSFET Qs (first MOSFET) of N-channel type (first conductivity type).
A word line selection voltage VCH is supplied from a word line selection voltage generation circuit VCHG described later to the drain and gate of the sense MOSFET Qs, and its source is coupled to the word line selection voltage generation circuit VCHG via the internal signal line MSO. .. Here, the sense MOSFET Qs has substantially the same size as the address selection MOSFET Qa forming the memory cell, and is formed under the same conditions as the address selection MOSFET Qa in the manufacturing process and the like. In addition, the sense MOSFET Qs is a memory array M.
By being formed in the ARY region, it receives the same substrate back bypass voltage as the address selection MOSFET Qa. As a result, the sense MOSFET Qs is assumed to have substantially the same threshold voltage as the address selection MOSFET Qa, and its value also exhibits substantially the same characteristic change due to the manufacturing process and the like. As will be apparent from the description below, the sense MOSFET Qs is functionally included in the word line selection voltage generation circuit VCHG described later.

The word lines W0 to Wm forming the memory array MARY are coupled to the word line drive circuit WD and are alternatively set to the selected state. The word line drive circuit WD is supplied with the word line selection voltage VCH from the word line selection voltage generation circuit VCHG and the internal control signal WPH from the timing generation circuit TG. Further, the X address decoder XD supplies m + 1-bit inverted word line selection signals WS0B to WSmB corresponding to the word lines W0 to Wm. The X address decoder XD is supplied with the internal address signals X0 to Xi of i + 1 bits from the X address buffer XB, and the internal control signal X from the timing generation circuit TG.
DG is supplied. Further, the X address buffer XB is supplied with the X address signals AX0 to AXi in a time division manner through the address input terminals A0 to Ai, and the timing generation circuit TG supplies the internal control signal XL. Here, the word line selection voltage VCH has a relatively high potential such as + 4.2V, which is higher than the internal power supply voltage VCL by about 0.9V, as its central value, as described later. Further, the internal control signal WPH is set to a low level like the ground potential of the normal circuit, and when the dynamic RAM is in the selected state, the word line selection voltage VCH is selectively selected at a predetermined timing.
It is a high level like. Inverted word line selection signal W
S0B to WSmB are normally set to a high level like the word line selection voltage VCH, and are alternatively set to a low level at a predetermined timing when the dynamic RAM is in a selected state and in accordance with the internal address signals X0 to Xi.

As shown in FIG. 3, the word line drive circuit WD includes m + 1 unit word line drive circuits U provided corresponding to the word lines W0 to Wm of the memory array MARY.
WD0 to UWDm are provided. Each of these unit word line drive circuits, as represented by the unit word line drive circuit UWD0, has P-channel MOSFETs Q3 and N provided in series between the word line selection voltage VCH and the ground potential of the circuit. Channel MOSFET Q11
including. The gates of these MOSFETs are coupled to the word line selection voltage VCH via two P-channel MOSFETs Q1 and Q2 arranged in parallel, and
Corresponding inverted word line selection signals WS0B to WSmB are supplied from the X address decoder XD. MOSFET Q
The commonly coupled drains of 3 and Q11 are MOSFE
The memory array M is coupled to the gate of TQ2.
It is coupled to the corresponding word lines W0 to Wm of ARY. The internal control signal WP is applied to the gate of the MOSFET Q1 that constitutes all the unit word line drive circuits UWD0 to UWDm.
H is commonly supplied.

When the dynamic RAM is in the non-selected state, the internal control signal WPH is set to the low level and the inverted word line selection signals WS0B to WSmB are all set to the high level like the word line selection voltage VCH as described above. To be done. Therefore, in the word line drive circuit WD, the MOSFs of all the unit word line drive circuits UWD0 to UWDm are
ETQ1 and Q11 are simultaneously turned on, and the word lines W0 to Wm of the memory array MARY are all brought to a low level, that is, a non-selection level like the ground potential of the circuit. The non-selection level of the word lines W0 to Wm is substantially M.
The gate potential of the corresponding MOSFET Q11 is surely brought to a high level like the word line selection voltage VCH by being fed back via the OSFET Q2.

On the other hand, when the dynamic RAM is selected, the internal control signal WPH changes to the word line selection voltage VC.
It is set to a high level like H and the inverted word line selection signal W
S0B to WSmB are alternatively set to the low level according to internal address signals X0 to Xi. Therefore, in the word line drive circuit WD, first, all unit word line drive circuits U
The MOSFET Q1 of WD0 to UWDm is turned off, and the low level of the inverted word line selection signals WS0B to WSmB is received, the MOSFET Q3 of the corresponding unit word line drive circuit is turned on alternatively to turn on the MOSF.
ETQ11 is alternatively turned off. As a result, one of the word lines W0 to Wm corresponding to the low-level inverted word line selection signal is alternatively set to the high level like the word line selection voltage VCH, that is, the selected state. That is, in the dynamic RAM of this embodiment, the predetermined word line selection voltage VCH is selectively transmitted according to the inverted word line selection signals WS0B to WSmB supplied from the X address decoder XD, so that the word line of the memory array MARY is transmitted. A so-called static word line selection method is adopted in which W0 to Wm are selectively set.

The X address decoder XD is selectively activated by setting the internal control signal XDG to a high level. In this operating state, the X address decoder XD decodes the internal address signals X0 to Xi,
The inverted word line selection signals WS0B to WSmB are alternatively set to the low level like the ground potential of the circuit. Further, the X address buffer XB is supplied with time-division X address signals AX0 to AX via address input terminals A0 to Ai.
i is fetched and held according to the internal control signal XL, and internal address signals X0 to Xi are formed based on these X address signals and supplied to the X address decoder XD.

Next, the complementary bit lines B0 * to Bn * forming the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SA, and further the complementary common data line CD.
Selectively connected to *. The sense amplifier SA includes n + 1 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY. These unit circuits each include a unit amplifier circuit formed by cross-coupling a pair of CMOS inverters, and a pair of switch MOSFETs provided between the complementary bit lines B0 * to Bn * and the complementary common data line CD *. Among these, each unit amplifier circuit is selectively and simultaneously operated by setting an internal control signal PA (not shown) to a high level,
Corresponding complementary bit line B0 from n + 1 memory cells coupled to the selected word line of memory array MARY
The minute read signal output via * to Bn * is amplified to be a high level or low level binary read signal. The switch MOSFET of each unit circuit is Y
The bit line selection signal supplied from the address decoder YD is selectively set to the high level to selectively turn on, and the complementary bit lines B0 * to Bn * and the common data line CD * corresponding to the memory array MARY are selectively turned on. And are selectively connected.

The Y address decoder YD has an internal address signal Y0 of i + 1 bits from the Y address buffer YB.
To Yi are supplied, and the internal control signal YDG is supplied from the timing generation circuit TG. The Y address buffer YB is supplied with the Y address signals AY0 to AYi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal YL.

The Y address decoder YD is selectively brought into an operating state by setting the internal control signal YDG to a high level. In this operating state, the Y address decoder YD decodes the internal address signals Y0 to Yi and selectively sets the bit line selection signal to the high level. Further, the Y address buffer YB has a Y address signal AY0 supplied via the address input terminals A0 to Ai.
To AYi are fetched and held according to the internal control signal YL, and internal address signals Y0 to Yi are formed on the basis of these Y address signals to generate a Y address decoder YD.
Supply to.

Complementary common data line CD * is coupled to data input / output circuit IO. The data input / output circuit IO includes a write amplifier, a main amplifier, a data input buffer and a data output buffer. Of these, the input terminal of the write amplifier is coupled to the output terminal of the data input buffer, and the output terminal thereof is coupled to the complementary common data line CD *. Further, the input terminal of the main amplifier is coupled to the complementary common data line CD *, and the output terminal thereof is coupled to the input terminal of the data output buffer. The input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal of the data output buffer is the data output terminal Dout.
Be combined with.

When the dynamic RAM is selected in the write mode, the data input buffer of the data input / output circuit IO takes in the write data supplied via the data input terminal Din and transfers it to the write amplifier. This write data is converted into a predetermined complementary write signal by the write amplifier, and is written in the selected one memory cell of the memory array MARY via the complementary common data line CD *. On the other hand, the main amplifier of the data input / output circuit IO is output from one selected memory cell of the memory array MARY via the complementary common data line CD * when the dynamic RAM is selected in the read mode. The read signal is further amplified and transmitted to the data output buffer. This read signal is sent to the outside from the data output buffer via the data output terminal Dout.

The timing generation circuit TG forms the above various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB which are externally supplied as a start control signal, and the dynamic generation is performed. Supply to each part of the type RAM.

The dynamic RAM of this embodiment further includes a step-down circuit VD and a word line selection voltage generation circuit VC.
With HG. Of these, the step-down circuit VD is supplied with the external power supply voltage VCC via the power supply voltage supply terminal VCC, and the word line selection voltage generation circuit VCHG is supplied with the internal power supply voltage VCL formed by the step-down circuit VD. .. Here, although the external power supply voltage VCC is not particularly limited, it is a positive power supply voltage having a relatively large absolute value such as + 5V, and the internal power supply voltage VCL is a positive power supply voltage having a relatively small absolute value such as + 3.3V. Power supply voltage.

The step-down circuit VD has a power supply voltage supply terminal VCC.
The internal power supply voltage VCL is formed by stepping down the external power supply voltage VCC supplied via the power supply voltage Vcc, and is supplied to each unit of the dynamic RAM as an operating power supply.

On the other hand, the word line selection voltage generation circuit VCHG
Is a sense MO formed in the internal signal line MSO, that is, in the region of the memory array MARY, as shown in FIG.
P-channel type (second conductivity type) MOSFET Q4 provided between the source of the SFET Qs and the ground potential of the circuit
(Second MOSFET) and N-channel MOSF
ETQ12 (third MOSFET) is included. These M
The internal power supply voltage VCL is commonly supplied to the gates of the OSFETs, and the commonly coupled drains thereof are coupled to the input terminal of the CMOS inverter N1. In addition, MOSF
ETQ4 is designed to have a relatively small threshold voltage Vthp, such as 0.2V, and the sense MOSFET
TQs is designed to have a relatively large threshold voltage Vthn such as 0.7V. In addition, MOSFETQ
4 is designed to have a relatively large conductance, and MOSFET Q12 is designed to have a relatively small conductance. This allows the MOSFE
TQ4 and Q12 are sense MOSFETs Qs and CM
Together with the OS inverter N1, the word line selection voltage VCH
To act as a level detection circuit LC for the output signal of the inverter N1, that is, the internal signal VC is selectively set to a high level.

That is, when the absolute value VCH of the word line selection voltage VCH is set to a relatively small value of VCH <VCL + Vthn + Vthp, the level detection circuit LC of the word line selection voltage generation circuit VCHG detects the sense MO.
SFETQs and MOSFETQ4 are turned off,
MOSFET Q12 is turned on. Therefore, M
The commonly coupled drain potentials of the OSFETs Q4 and Q12 become a low level like the ground potential of the circuit, which causes the output signal of the inverter N1, that is, the internal signal V
C is set to high level. On the other hand, the word line selection voltage VC
When the absolute value VCH of H is set to a relatively large value of VCH> VCL + Vthn + Vthp, in the level detection circuit LC, both the sense MOSFET Qs and the MOSFET Q4 are turned on, and the MOSFET Q12 is also turned on. As described above, the MOSFET Q4 is assumed to have a relatively large conductance, and the MOSFET Q12
Has a relatively small conductance. Thus, the commonly coupled drain potentials of MOSFETs Q4 and Q12 are
Becomes a relatively high level which is determined by the conductance ratio of, and the output signal of the inverter N1, that is, the internal signal VC is brought to a low level.

The word line selection voltage generation circuit VCHG further includes a voltage generation circuit VG that receives the output signal of the level detection circuit LC, that is, the internal signal VC. The voltage generation circuit VG is selectively operated under the condition that the internal signal VC is at a high level, and replenishes the potential of the word line selection voltage VCH to push it up to a predetermined level. As a result, the potential of the word line selection voltage VCH, that is, the absolute value VC
H is controlled to converge to VCH≈VCL + Vthn + Vthp, that is, approximately + 4.2V.

As described above, the MOSFET forming the level detection circuit LC of the word line selection voltage generation circuit VCHG.
Q4 is designed to have a relatively small threshold voltage, and sense MOSFET Qs is designed to have a relatively large threshold voltage. Furthermore, sense MOSFE
TQs are formed in the area of the memory array MARY,
The threshold voltage has substantially the same absolute value as the address selection MOSFET Qa forming the memory cell, and exhibits substantially the same characteristic change depending on the manufacturing process. In other words, the absolute value of the word line selection voltage VCH can be made extremely close to the value obtained by adding the threshold voltage of the address selection MOSFET Qa to the absolute value of the power supply voltage of the memory array MARY and the peripheral circuits, that is, the internal power supply voltage VCL. This makes it possible to sufficiently compress the potential margin of the word line selection voltage VCH and reduce its absolute value. As a result, it is possible to reduce the charge or discharge current associated with the level change of the word line or the like, and promote the reduction in power consumption of the dynamic RAM.

By applying the present invention to a semiconductor memory device such as a dynamic RAM adopting the static word line selection system as shown in the above embodiment, the following operational effects can be obtained. That is, (1) a word line selection voltage generating circuit such as a dynamic RAM adopting a static word line selection system is
N which receives the word line selection voltage at its drain and gate
Channel type sense MOSFET and sense MOSF
A pair of P-channel and N-channel MOSFETs provided in series between the source of ET and the ground potential of the circuit and commonly receiving a predetermined internal power supply voltage at their gates, and a common combination of these P-channel and N-channel MOSFETs. A level detection circuit including a CMOS inverter for receiving the output drain potential, and a voltage detection circuit for selectively replenishing the potential of the word line selection voltage according to the output signal of the level detection circuit. And the sense MOSFET is formed in the memory array region under the same conditions as the address selection MOSFET forming the memory cell, and the absolute value of the threshold voltage of the sense MOSFET and its characteristic change are detected. Address selection MOSF
It is possible to obtain the effect that it can be almost matched with ET.

(2) According to the above item (1), the potential margin of the word line selection voltage can be compressed and its absolute value can be reduced. (3) According to the above items (1) and (2), it is possible to reduce the charge or discharge current associated with the level change of the word line or the like. (4) According to the above items (1) to (3), it is possible to obtain an effect that the power consumption of the dynamic RAM adopting the static word line selection method can be promoted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM memory array MARY can be divided into a plurality of sub memory arrays or memory mats. In this case, the sense MO is divided into a plurality of divided sub memory arrays or memory mats.
SFETQs are provided, and, for example, these sense MOSFEs are
The voltage generation circuit VG may be selectively activated by the logical sum of the sense results of TQs. The dynamic RAM can adopt the shared sense method,
Adopting the address multiplex method is not a necessary condition either. The dynamic RAM can have a so-called multi-bit configuration that inputs or outputs a plurality of bits of stored data at the same time, and its block configuration is not restricted by this embodiment. Further, a specific circuit configuration of the memory array MARY and the word line drive circuit WD and the word line selection voltage generation circuit VCHG shown in FIGS. 2 and 3 and FIG. 4, combinations of internal control signals, etc., polarity of power supply voltage and MOSFET Various conductivity types and the like can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to, for example, a pseudo static RAM having a dynamic RAM as a basic configuration and various digital integrated circuit devices including these memories. The effect of the present invention is further exerted in the pseudo static RAM in which the power consumption is an important factor. The present invention can be widely applied to at least a semiconductor memory device adopting the static word line selection method and a semiconductor device incorporating such a semiconductor memory device.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a word line selection voltage generating circuit such as a dynamic RAM adopting a static word line selection system is provided, for example, in an N-channel type sense MOSFE which receives the word line selection voltage at its drain and gate.
T, a pair of P-channel and N-channel MOSFETs provided in series between the source of the sense MOSFET and the ground potential of the circuit and commonly receiving a predetermined internal power supply voltage at their gates, and these P-channel and N-channel A level detection circuit including a CMOS inverter that receives a drain potential commonly connected to the MOSFETs and using the output signal of the CMOS inverter as its output signal, and the potential of the word line selection voltage is selectively supplemented according to the output signal of the level detection circuit. By forming the sense MOSFET under the same conditions as the address selection MOSFET forming the memory cell and in the memory array region, the absolute value of the threshold voltage of the sense MOSFET and its characteristic change. To select an address M which constitutes a memory cell It can be substantially matched with the SFET. Accordingly, the potential margin of the word line selection voltage can be correspondingly compressed and its absolute value can be reduced. As a result, it is possible to reduce the charge or discharge current associated with the level change of the word line or the like, and promote the low power consumption of the dynamic RAM or the like adopting the static word line selection method.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing an embodiment of a memory array included in the dynamic RAM of FIG.

3 is a circuit diagram showing an embodiment of a word line drive circuit included in the dynamic RAM of FIG.

4 is a circuit diagram showing an embodiment of a word line selection voltage generation circuit included in the dynamic RAM of FIG.

[Explanation of symbols]

MARY ... Memory array, SA ... Sense amplifier, WD ... Word line drive circuit, XD ... X address decoder, YD ... Y address decoder, XB ...
X address buffer, YB ... Y address buffer, IO ... Data input / output circuit, TG ... Timing generation circuit, VD ... Step-down circuit, VCHG ... Word line selection voltage generation circuit. W0 to Wm ... Word line, B
0 * to Bn * ... Complementary bit line, Cs ... Information storage capacitor, Qa ... Address selection MOSFET, Q
s ... Sense MOSFET. UWD0 to UWDm ...
-Unit word line drive circuit. LC: Level detection circuit,
VG ... Voltage generation circuit. Q1-Q4 ... P-channel MOSFET, Q11-Q12 ... N-channel M
OSFET, N1 ... CMOS inverter.

Claims (3)

[Claims] 1. A memory array including word lines and bit lines arranged orthogonally, and memory cells arranged in a lattice at intersections of these word lines and bit lines, and a MOSFET which constitutes the memory cells. Including a sense MOSFET formed under the conditions, the potential of which is the sense M
A word line selection voltage generating circuit that forms a word line selection voltage that changes in accordance with a change in the characteristics of the OSFET, and selectively transfers the word line selection voltage to selectively select the word line. And a word line driving circuit for controlling the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the sense MOSFET is formed in a region of the memory array. 3. The sense MOSFET comprises a first MOSFET of a first conductivity type that receives the word line selection voltage at its drain and gate, and the word line selection voltage generation circuit comprises the sense MOSFET. Second MOSFET of the second conductivity type and a third M of the first conductivity type which are provided in series between the source and the ground potential of the circuit and whose gate commonly receives a predetermined internal power supply voltage.
A level detection circuit that includes an OSFET and a CMOS inverter that receives the drain potentials of the second and third MOSFETs commonly coupled to each other, and that uses the output signal of the CMOS inverter as its output signal, and the output signal of the level detection circuit 3. The semiconductor memory device according to claim 1, further comprising a voltage generation circuit that selectively corrects the potential of the word line selection voltage in accordance with the above.