JPH05129329A - Manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To control a threshold voltage with an excellent controllability by a method wherein fluorine ions are implanted, by making use of a resist pattern and a gate electrode as masks, into regions in which a source and a drain are to be formed, the resist pattern is removed and, after that, boron ions are implanted into the gate electrode and the regions in which the source and the drain are to be formed. CONSTITUTION:A gate insulating film 2 and a conductive film 3 are formed sequentially on an n-type semiconductor region 1; the conductive film 3 is etched by making use of a resist pattern 4 as a mask. Thereby, a gate electrode 5 is formed. Then, fluorine ions 100 are implanted, by msking use of the resist pattern 4 and the gate electrode 5 as masks, into regions X in which a source and a drain are to be formed. Then, the resist pattern 4 is removed; after that, boron ions 200 are implanted into the gate electrode 5 and the regions X in which the source and the drain are to be formed. For example, a gate electrode 5 is formed of polycrystalline silicon, the implantation quantity of boron ions is 10<15>cm<-2> or above and the implantation quantity of fluorine ions is two times as much or above the implantation quantity of boron ions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MIS transistor incorporated in an integrated circuit.

[0002]

2. Description of the Related Art With the miniaturization of integrated circuits, the electric field applied to a device at a constant power supply voltage has become stronger. In addition, the number of elements integrated per unit area has increased, and the power consumption per unit area has also increased.
In order to solve these problems, it is effective to lower the power supply voltage of the integrated circuit, and in recent years, there is a trend to reduce the standard power supply voltage from the conventional 5 [V] to about 3 [V]. Can be seen.

In a so-called complementary integrated circuit, in order to reduce the power supply voltage and ensure the operating speed of the circuit,
It is necessary to lower the threshold voltage of the MIS transistor.
Furthermore, in order to lower the threshold voltage and control it accurately, it is necessary to make the MIS transistor a surface channel type. Hereinafter, a conventional method for manufacturing a MIS transistor will be described.

2A to 2D are cross-sectional views in order of steps, showing a conventional method for manufacturing a MIS transistor. First, FIG.
As shown in (a), a thickness of 1 is formed on the n-type silicon substrate 11.
A gate oxide film 12 made of a silicon oxide film having a thickness of about 5 [nm] and a polycrystalline silicon film 13 having a thickness of about 300 [nm] are sequentially laminated and formed.
A resist pattern 14 for forming a gate electrode is formed on the surface 3.

Next, as shown in FIG. 2B, the polycrystalline silicon film 13 is etched by a well-known dry etching technique using the resist pattern 14 as a mask to form a gate electrode 15. Next, as shown in FIG. 2C, after removing the resist pattern 14, 30 [keV] is applied to the entire surface.
Boron fluoride ion (BF ₂ ⁺ ) 300 of about 5 × 10 ¹⁵ [cm ⁻² ] is implanted with an acceleration energy of about. As described above, the boron fluoride ion (BF ₂ ⁺ ) 300 is used as the p-type impurity ion because the boron fluoride ion 300 has a larger mass than the boron ion and thus has a small projection range. This is because the channeling phenomenon is unlikely to occur.

Thereafter, as shown in FIG. 2 (d), the whole body is irradiated with infrared rays to heat the temperature to about 1000 ° C. and activate the implanted boron. This allows
A p-type diffusion layer 16 is formed in the n-type silicon substrate 11. In the silicon substrate 11, the presence of fluorine atoms suppresses the diffusion of boron atoms, so that the diffusion layer 16 becomes shallow. At the same time, the gate electrode 15 also becomes p-type, and a surface channel MIS transistor is formed.

[0007]

However, according to our research, it is known that the presence of fluorine atoms promotes the diffusion of boron atoms in the silicon oxide film. That is, in the conventional MIS transistor manufacturing method, the diffusion of boron atoms in the gate oxide film 12 made of a silicon oxide film in contact with the gate electrode 15 is promoted by the fluorine atoms present in the gate electrode 15. Therefore, the boron atom in the gate electrode 15 permeates the gate oxide film 12 and the silicon substrate 1
There is a problem in that the impurity concentration near the surface of the silicon substrate 11 immediately below the gate electrode 15 is changed due to reaching the surface of No. 1. The degree of permeation of boron atoms from the gate electrode 15 into the silicon substrate 11 depends on the thickness of the gate oxide film 12 and the thickness of the gate electrode 15, etc., and thus it is difficult to control with high precision. However, there is a problem that the controllability of the threshold voltage is deteriorated.

In view of the above problems, an object of the present invention is to provide a method of manufacturing a MIS transistor which can control the threshold voltage with high accuracy.

[0009]

A method of manufacturing a MIS transistor according to claim 1 is as follows. A gate insulating film and a conductive film are sequentially formed on the n-type semiconductor region.
A gate electrode is formed by etching the conductive film using the resist pattern as a mask. Fluorine ions are implanted into the source / drain formation planned regions using the resist pattern and the gate electrode as a mask. After removing the resist pattern, boron ions are implanted into the gate electrode and the source / drain formation planned regions.

A method of manufacturing a MIS transistor according to a second aspect is the method of manufacturing a MIS transistor according to the first aspect, characterized in that at least a portion of the gate electrode in contact with the gate insulating film is made of polycrystalline silicon. A method for manufacturing a MIS transistor according to claim 3 is the method according to claim 1.
Alternatively, in the method for manufacturing a MIS transistor described in 2, the boron ion implantation amount is 10 ¹⁵ [cm ⁻² ] or more, and the fluorine ion implantation amount is twice or more the boron ion implantation amount. To do.

[0011]

According to the structure of the present invention, fluorine ions are implanted into the source / drain formation planned regions by using the resist pattern and the gate electrode as a mask, and after removing the resist pattern, boron ions are implanted into the gate electrode and the source / drain formation planned regions. By injecting, since there is no fluorine atom in the gate electrode, the diffusion of boron atoms in the gate insulating film in contact with the gate electrode is not promoted unlike in the conventional case, and the boron atom in the gate electrode is not promoted. Can be prevented from penetrating the gate insulating film and reaching the semiconductor region. As a result, the impurity concentration of the semiconductor region immediately below the gate electrode can be controlled with high accuracy. Further, the diffusion of boron atoms in the source / drain formation planned regions can be suppressed by the fluorine atoms existing in the source / drain formation planned regions.

[0012]

1 (a) to 1 (d) show an MI of an embodiment of the present invention.
FIG. 9 is a cross-sectional view in order of the steps, showing a method for manufacturing an S transistor.
First, as shown in FIG. 1 (a), a gate insulating film having a thickness of 15 [n is formed on an n-type silicon substrate 1 to be a semiconductor region.
m] and a thickness of 30 to form the gate oxide film 2 and the conductive film.
A polycrystalline silicon film 3 having a thickness of about 0 [nm] is sequentially laminated and formed, and a resist pattern 4 for forming a gate electrode is further formed on the polycrystalline silicon film 3.

Next, as shown in FIG. 1 (b), the polycrystalline silicon film 3 is etched by the well-known dry etching technique using the resist pattern 4 as a mask to form the gate electrode 5.
After forming the resist pattern 4 and the gate electrode 5
Fluorine ions 100 are implanted into the source / drain formation planned region X in the silicon substrate 1 using the mask as a mask. By the implantation of the fluorine ions 100, the silicon bond is broken in the vicinity of the surface of the silicon substrate 1 to be in an amorphous state. In addition, at this time, the implantation amount of the fluorine ion 100 is the same as that of the boron ion to be implanted later (reference numeral 20 in FIG. 1C).
0) more than twice. As a result, the effect of suppressing the diffusion of boron atoms in the silicon substrate 1 becomes large. It is desirable that the specific implantation amount of the fluorine ion 100 is about 10 ¹⁶ [cm ⁻² ].

Next, as shown in FIG. 1 (c), after removing the resist pattern 4, 5 × 10 ¹⁵ [cm ^{− is} applied to the gate electrode and the region where the source / drain is to be formed with an acceleration energy of about 10 [keV]. ² ] Boron ion 200 of about ² ] is implanted. The implantation amount of the boron ions 200 needs to be larger than about 10 ¹⁵ [cm ⁻² ] in order to sufficiently reduce the sheet resistance of the diffusion layer, but 5 × 10 ¹⁵ [cm ⁻² ].
If it is more than the above range, the sheet resistance is saturated and does not become so low, and rather the diffusion layer tends to become deep, which is not preferable. The boron ion 200 is an ion that easily causes a channeling phenomenon due to its small mass. Here, the vicinity of the surface of the silicon substrate 1 is made amorphous by the implantation of the fluorine ion 100 performed in the step shown in FIG. 1 (b). Therefore, the channeling phenomenon of the boron ion 200 does not occur. As a result, the distribution of boron atoms does not spread deeply in the silicon substrate 1.

Thereafter, as shown in FIG. 1 (d), the entire surface is irradiated with infrared rays to be heated to a temperature of about 1000 ° C. to activate the implanted boron atoms. On this occasion,
Since a large amount of fluorine atoms are present in the silicon substrate 1, the diffusion of boron atoms is suppressed and 0.2 to 0.3 [μ
A very shallow p ⁺ type diffusion layer 6 of [m] is formed. Thereby, the short channel effect can be suppressed.

On the other hand, since fluorine atoms are not injected into the gate electrode 5, boron atoms diffuse in the gate oxide film 2 due to the original diffusion coefficient, and boron atoms are present in a large amount as compared with the case where a large amount of fluorine atoms are present. Atoms are unlikely to penetrate into the silicon substrate 1. As a result, the impurity concentration of the silicon substrate 1 immediately below the gate oxide film 2, that is, the channel impurity concentration of the MIS transistor can be controlled accurately, and the threshold voltage can be controlled accurately.

Although the MIS transistor is formed in the n-type silicon substrate 1 in the embodiment, it is an n-type diffusion layer formed in the p-type silicon substrate, that is, an n-type diffusion layer.
The same effect can be obtained by forming the well or the n-well forming the twin tub. Although the material of the gate electrode 5 is polycrystal silicon, it may have a so-called polycide structure in which a metal silicide film is laminated on the polycrystal silicon film. In this case, the film of the polycrystal silicon film is formed by the conventional manufacturing method. Since the thickness is small, it becomes easier for boron atoms to penetrate the gate oxide film 2. However, if the manufacturing method of the present invention is applied, the penetration of boron atoms can be effectively suppressed. Further, the film thicknesses of the gate oxide film 2 and the polycrystalline silicon film 3 are arbitrary.

[0018]

According to the method of manufacturing a MIS transistor of the present invention, fluorine ions are implanted into the source / drain formation planned regions by using the resist pattern and the gate electrode as a mask, and after removing the resist pattern, the gate electrode and the source / drain are formed. By implanting boron ions in the region to be formed, since there are no fluorine atoms in the gate electrode, diffusion of boron atoms is not promoted in the gate insulating film in contact with the gate electrode as in the conventional case,
It is possible to prevent boron in the gate electrode from penetrating the gate insulating film and reaching the semiconductor region. As a result, the impurity concentration of the semiconductor region immediately below the gate electrode can be controlled with high accuracy. Further, the diffusion of boron atoms in the source / drain formation planned regions can be suppressed by the fluorine atoms existing in the source / drain formation planned regions.

As a result, the threshold voltage can be controlled with high accuracy, and the shallow diffusion layers serving as the source / drain can be formed. As a result, a surface channel MIS transistor having a low threshold voltage suitable for low voltage operation and suppressing the short channel effect can be obtained.

[Brief description of drawings]

FIG. 1 is a step-by-step cross-sectional view showing a method of manufacturing a MIS transistor of one embodiment of the present invention.

2A to 2D are cross-sectional views in order of the steps, showing a conventional method for manufacturing a MIS transistor.

[Explanation of symbols]

 1 Silicon substrate (semiconductor region) 2 Gate oxide film (gate insulating film) 3 Polycrystalline silicon film (conductive film) 4 Resist pattern 5 Gate electrode 100 Fluorine ion 200 Boron ion X Source / drain formation planned region

Claims (3)

[Claims] 1. A step of sequentially forming a gate insulating film and a conductive film on an n-type semiconductor region, a step of forming a gate electrode by etching the conductive film using a resist pattern as a mask, the resist pattern, and MIS including: a step of implanting fluorine ions into the source / drain formation planned regions using the gate electrode as a mask; and a step of implanting boron ions into the gate electrodes and the source / drain formation planned regions after removing the resist pattern. Method of manufacturing transistor. 2. The method for manufacturing a MIS transistor according to claim 1, wherein at least a portion of the gate electrode in contact with the gate insulating film is made of polycrystalline silicon. 3. The implantation amount of boron ions is 10 ¹⁵ [c
m ⁻² ] or more, and the amount of fluorine ion implantation is twice or more the amount of boron ion implantation. 3. The method for manufacturing a MIS transistor according to claim 1, wherein