JPH05122081A - Pulse width modulator - Google Patents

Abstract

PURPOSE:To improve the efficiency of a D/A converter by optionally outputting the signals from the flat PWM output signals 'LL-LL' of an 'L' level to the flat PWM output signals 'HH-HH' of an 'H' level in a pulse width modulator. CONSTITUTION:The modulator includes an input data register 90 storing digital input data 54, a pulse width generator 50 outputting generator output signal 56 which is pulse-width-modulated based on input data 54 from the input data registor 90, and a selector part 58 receiving a generator output signal from the pulse width generator 50 and a selector part control signal 62. The selector part 58 outputs either of the generator output signal 56 or the flat signal of 'H' or 'L' level based on a selector part control signal 62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a pulse width modulator (P
WM: Pulse Width Modulator device).

Conventionally, PWM is generally used as a D / A converter.
A device is used, and in this PWM device, when n-bit input data is D / A converted, there are 2 ⁿ types of waveforms that can be output. That is, as the waveform that can be output, a flat waveform of "L" level ("LL ... LL")
2 ⁿ types of waveforms (“HH ... HHL”), or
There are 2 ⁿ waveforms (“HLL ... LL”) to “H” level flat waveforms (“HH ... HH”), and 2 ⁿ types of D / A conversion are possible. However, there are 2 ⁿ +1 types of waveforms required for arbitrary output from "L" level flat waveforms ("LL ... LL") to "H" level flat waveforms ("HH ... HH"). Is. Therefore, in the conventional PWM device, one kind of required waveform is insufficient, and there is a problem that the efficiency of D / A conversion is low.

Then, by arbitrarily outputting from the flat waveform of "L" level ("LL ... LL") to the flat waveform of "H" level ("HH ... HH"), D
It is desired to improve the efficiency of / A conversion.

[0004]

2. Description of the Related Art FIG. 5 shows a conventional pulse width modulator. In FIG. 5A, the pulse width modulator includes a pulse width generator 10, and the pulse width generator 10
Pulse-width-modulates the digital input data 14 while being synchronized with the input clock 12, and outputs the pulse-width-modulated PWM output signal 16.

FIG. 5 (B) shows a timing chart of the pulse width modulator of FIG. 5 (A). In FIG. 5B, the case where the 2-bit input data 14 is pulse-width modulated is shown, and one input data 1 is input at times t _{1 to} t _4.
4 is pulse width modulated, and similarly, one input data 14 is pulse width modulated at times t _{5 to} t ₈ . here,
Considering the times t _{1 to} t ₄ , when the input data 14 is “00”, the PWM output signal 16 at the “L” level is output at all of the times t _{1 to} t ₄ , and the input data 14 is “0”. 01 ", the time t _1" PWM output signal 16 is L "level" in and time t ₂ ~t ₄ at level "H is outputted. Similarly, when the input data 14 "10" is output PWM output signal 16 is at "L" level at time t ₁ ~t a ₂ "H" level time t ₃ ~t _4, If the input data 14 "11", PWM output signal 16 is output is at "L" level and time t ₄ at the "H" level at time t ₁ ~t _3.

As described above, according to the pulse width modulator of FIG. 5, 2-bit input data 14 ("00", "0") is input.
1 ”,“ 10 ”,“ 11 ”) can be pulse-width modulated into four types of PWM output signals 16.

Next, FIG. 6 shows the pulse width modulator of FIG. 5 in detail. In FIG. 6A, the frequency divider circuit 18 includes a first frequency divider 20 and a second frequency divider 20 connected in series.
The frequency divider 22 is included. The first frequency divider 20 has an input pulse 2
4, the first frequency divider 20 supplies the first clock 26 to the second frequency divider 22 based on the input pulse 24,
The second frequency divider 22 outputs a second clock based on the first clock 26.
The clock 28 is output. Then, the input clock 12 is constituted by the first clock 26 and the second clock 28, and the input clock 12 is supplied to the pulse width generator 10. In addition, the pulse width generator 10 has a lower bit 1
2 bits of input data 14 consisting of 4a and upper bits 14b are supplied, and the pulse width generator 10 performs pulse width modulation of the input data 14 and outputs a PWM output signal 16 while being synchronized by the input clock 12. To do.

Below, the timing chart of FIG.
Referring to the operation of the pulse width modulator of FIG.
explain. The input clock 12 is the first clock 26 and
It is composed of a second clock 28, and the first clock 26 is
Time t₁, T₃, T_Five, T₇At "H" level,
Interval t₂, T_Four, T₆, T₈, T_TenAt "L" level
It The second clock 28 also divides the first clock 26.
It is a cycle (see FIG. 6A), and time t₁~
t ₂, T_Five~ T₆, T₉~ T_TenIs at "H" level,
Time t₃~ T_Four, T₇~ T ₈Is at the "L" level.

In FIG. 6B, 2-bit input data 1
4 is shown in the case of performing pulse width modulation, and time t ₁ to
One input data 14 is pulse-width modulated at t ₄ , and similarly, one input data 14 is pulse-width modulated at times t _{5 to} t ₈ . Here, since the pulse width modulation at times t _{1 to} t ₄ and the pulse width modulation at times t _{5 to} t ₈ are similar, pulse width modulation at times t _{1 to} t ₄ will be considered below.

When the input data 14 is "00", P
The WM output signal 16 has a time t₁~ T _Four"L" level in all of
The bell. When the input data 14 is “01”, P
The WM output signal 16 is timed based on the first clock 26.
t₁Is at the "H" level.

When the input data 14 is "10", P
The WM output signal 16 is at the “H” level from time t _{1 to} t ₂ based on the second clock 28. When the input data 14 is “11”, the PWM output signal 16 is based on the first clock 26 and the second clock 28, and the time t _{1 to} t
It is "H" level at ₃ .

As described above, the pulse width modulator of FIG.
According to the first clock 26 and the second clock 28,
The 2-bit input data 14 (“00”, “0”
1 ”,“ 10 ”,“ 11 ”) 4 types of PWM output signals
16 (time t₁~ T_FourAt "L" level, time t₁so
"H" level, time t₁~ T₂At "H" level, time t
₁~ T ₃Pulse width modulation to “H” level)
Wear.

[0013]

In the conventional pulse width modulator, when n-bit input data is pulse width modulated, 2 ⁿ kinds of PWM output signals can be obtained.
However, from the flat PWM output signal (“LL ... LL”) of “L” level to the flat PW of “H” level.
Considering the case where it is desired to arbitrarily output up to the M output signals (“HH ... HH”), the required PWM output signal is 2 ⁿ +
There is one type.

Therefore, in the conventional pulse width modulator,
(2 ⁿ +1) would be -2 ⁿ = 1 i.e. the one of the PWM output signal is insufficient, there is a problem of low efficiency of the D / A converter.

The above problems will be described in detail with reference to the pulse width modulators of FIGS. 5 and 6. In the pulse width modulator of FIGS. 5 and 6, the 2-bit input data 14 (“00”,
4 types of PWM output signals 16 (“LLLL”, “HLLL”, “HHL”) from “01”, “10”, “11”)
L "," HHHL ") can be obtained (Fig. 5
(B) and FIG. 6 (B)). However, from the flat PWM output signal 16 (“LLLL”) of “L” level to the flat PWM output signal 16 of “H” level (“HH”
Considering the case where it is desired to arbitrarily output up to HH ″), five types of PWM output signals 16 are required.
LL ”,“ HLLL ”,“ HHLL ”,“ HHHL ”,
Five types of PWM output signals 16 of "HHHH" are required.

Therefore, in the pulse width modulator of FIGS. 5 and 6, 5-4 = 1, that is, one type of PWM output signal 16 is insufficient, and the efficiency of D / A conversion is low. Specifically, reference numeral 3 is used in each of FIG. 5B and FIG.
“HHHH” PWM output signal 16 indicated by 0 and 32
Will run short.

The present invention has been made in view of the above problems, and an object thereof is from a flat PWM output signal of "L" level ("LL ... LL") to a flat PWM output signal of "H" level. (EN) It is possible to provide a pulse width modulation device capable of improving the efficiency of D / A conversion by arbitrarily outputting ("HH ... HH").

[0018]

The present invention provides an input data register (9) for storing digital input data (54).
0) and the input signal (54) from the input data register (90), the pulse width modulated output signal (5
6) which outputs 6), and a selector section (58) which receives the generator output signal (56) and the selector section control signal (62) from the pulse width generator (50)
And the selector section (58) outputs either the generator output signal (56) or a flat signal of "H" or "L" level based on the selector section control signal (62). It is characterized in that it is configured to.

[0019]

First, considering the case where the pulse width generator (50) outputs from the "L" level flat output signal (56) to the "HH ... HHL" output signal (56), the selector section (58). Is an output signal (56) from the pulse width generator (50) based on the selector control signal (62),
Alternatively, one of the "H" level flat signals is output as the PWM output signal (64). On the other hand, when the pulse width generator (50) outputs from the "HLL ... LL" output signal (56) to the "H" level flat output signal (56), the selector section (58).
Is an output signal (56) from the pulse width generator (50) based on the selector control signal (62), or
One of the flat signals of the “L” level is set to P
It outputs as a WM output signal (64).

As described above, in the present invention, the selector unit (58) is connected to the pulse width generator (50), and the selector unit (58) receives the pulse width based on the selector unit control signal (62). Since the generator (50) can output the lacking "H" or "L" level flat signal, the "L" level flat PWM output signal (64) ("LL ... LL") An "H" level flat PWM output signal (64) ("HH ... HH") can be arbitrarily output.

The flat signal of "H" or "L" level output from the selector unit (58) may be obtained from the outside of the selector unit (58) or the selector unit control signal (62). ) Itself.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a pulse width modulator according to an embodiment of the present invention.

In FIG. 1A, a pulse width generator 50
Pulse-width-modulates the digital input data 54 while being synchronized with the input clock 52, and outputs the pulse-width-modulated output signal 56. This output signal 56
Is supplied to the selector unit 58, and the selector unit 58
Is supplied with a flat signal of "H" or "L" level, in the embodiment a fixed signal 60 of "H" level. Based on the selector control signal 62, the selector 58 outputs either the output signal 56 from the pulse width generator 50 or the “H” level fixed signal 60 to PW.
It is output as the M output signal 64. The selector unit 58
Is schematically shown as a switch in FIG. 1A, but may be an electric switching element.

The operation of the pulse width modulator of FIG. 1A will be described below with reference to the timing chart of FIG. In FIG. 1B, 2-bit input data 54
Pulse width modulation is shown, and the time t _{1 to} t
₄ with one of the input data 54 is pulse width modulated, in a similar manner, one input data 54 at time t ₅ ~t ₈ is pulse width modulated. Here, since the pulse width modulation at times t _{1 to} t ₄ and the pulse width modulation at times t _{5 to} t ₈ are similar, pulse width modulation at times t _{1 to} t ₄ will be considered below.

First, when the selector unit control signal 62 is at "L" level, the selector unit 58 outputs the output signal 56 from the pulse width generator 50 as the PWM output signal 64. That is, when the input data 54 is “00”, the PWM output signal 64 is at “L” level during all of the times t _{1 to} t ₄ , and the input data 14 is “01”, “1”.
0 "," 11 "in the case of the PWM output signal 64, respectively the time t _1" H "level at time t ₁ ~t _2" H "level at time t ₁ ~t _3" H "level Is.

Next, the PWM output signal 64 is changed from time t ₁ to t.
_When it is desired to set all ₄ to "H" level, the pulse width generator 50 cannot generate such a flat signal of "H" level. Therefore, when the selector unit control signal 62 is set to the “H” level, the selector unit 58
Is the PWM output signal 64 for the "H" level fixed signal 60.
Output as. Thus, PWM output signal 64 is obtained at "H" level at all times t ₁ ~t _4.

As described above, according to the pulse width modulator of the embodiment of the present invention, the flat PW of "L" level is obtained.
The M output signal (“LLLL”) to the “H” level flat PWM output signal (“HHHH”) can be arbitrarily output.

Next, FIG. 2 shows details of the pulse width modulator of FIG. In FIG. 2, the selector unit 58 includes two AND gates 66 and 68, one OR gate 70, and one inverter (inverting circuit) 72. The output signal 56 from the pulse width generator 50 is supplied to one input end of the AND gate 66, and the fixed signal 60 of "H" is supplied to one input end of the AND gate 68. The selector unit control signal 62 is supplied to the other input end of the AND gate 66 via the inverter 72, and the selector unit control signal 62 is supplied as it is to the other input end of the AND gate 68. Either one of the AND gates 66 and 68 is enabled depending on whether 62 is at "L" level or "H" level. And gates 66 and 68
Is supplied to an OR gate 70, which outputs one of the outputs from the AND gates 66 and 68 as a PWM output signal 64.

In the above structure, when the selector control signal 62 is at "L" level, the OR gate 66 is in the valid state and the OR gate 68 is in the invalid state. Therefore, the output signal 56 from the pulse width generator 50 passes through the AND gate 66 and is output from the OR gate 70 as the PWM output signal 64. On the other hand, the selector control signal 6
When 2 is at "H" level, the OR gate 66 is in the invalid state and the OR gate 68 is in the valid state. Therefore, the “H” level fixed signal 60 passes through the AND gate 68 and is output from the OR gate 70 as the PWM output signal 64.

As described above, according to the selector section 58 shown in FIG. 2, either the generator output signal 56 or the "H" level fixed signal 60 is supplied to the PWM output signal 64 based on the selector section control signal 62. Can be output as

In the above embodiment, the pulse width generator 50 outputs from the flat output signal 56 of "L" level to the output signal 56 of "HHHL", so that the fixed signal 60 lacks "H". Although the signal has a flat level, the pulse width generator 50 outputs the signal "HLLL" 5
When outputting from 6 to the "H" level flat output signal 56, the fixed signal 60 is a lacking "L" level flat signal.

Further, in the above embodiment, the flat signal of "H" level is supplied from the outside of the selector section 58 to "H".
Although it is obtained as the fixed signal 60 of the level, in the present invention, a flat signal of "H" or "L" level can be obtained from the selector control signal 62 itself. An example of this is shown in FIG.

In FIG. 3A, the pulse width generator 50
From the flat output signal 56 of "L" level to "HH
It outputs up to the output signal 56 of "HL". Selector unit 58
Includes an OR gate 74, the output signal 56 is supplied to one input terminal of the OR gate 74, and the selector unit control signal 62 is supplied to the other input terminal of the OR gate 74. Then, the selector control signal 62 is "L".
If it is at the level, the OR gate 74 outputs the generator output signal 56 as it is as the PWM output signal 64. On the other hand, when the selector unit control signal 62 is at "H" level, the OR gate 74 outputs the "H" level control signal 62 as it is as the PWM output signal, whereby the "H" level flat signal is output. Is obtained.

Further, in FIG. 3B, the pulse width generator 50 outputs the "HLLL" output signal 56 to the "H" level flat output signal 56. The selector unit 58 includes an AND gate 76, and the AND gate 76
The output signal 56 is supplied to one of the input terminals, and the selector control signal 62 is supplied to the other input terminal of the AND gate 76. Then, the selector control signal 6
If 2 is at "H" level, AND gate 76
Is the PWM output signal 64 without changing the generator output signal 56.
Output as. On the other hand, when the selector unit control signal 62 is at “L” level, the AND gate 76
The "L" level control signal 62 is directly output as a PWM output signal, whereby an "L" level flat signal is obtained.

As described above, according to the pulse width modulator shown in FIG. 3, the selector unit control signal 62 itself receives the fixed signal of "H" or "L" level from the outside of the selector unit 58. A flat signal of "H" or "L" level can be obtained.

Next, FIG. 4 shows a specific circuit configuration to which the pulse width modulator according to the embodiment of the present invention is applied. In FIG. 4, reference numeral 78 indicates a bus, and the bus 7
8 stores the control signal 80 in the control register 82, which supplies the control signal 84 to the pulse width generator 50 to control the generator 50. Also, the bus 78 is n +
The data 86 consisting of 1 bit is supplied to the data register section 88, and the n-bit input data of the data 86 is n
The bit input data register 90 stores the 1-bit selector section control signal of the data 86, and the 1-bit selector section control register 92 stores the 1-bit selector section control signal.

The pulse width generator 50 has a control signal 84
The pulse width modulation is performed on the n-bit input data 54 from the input data register 90 and the pulse width modulated output signal 56 is output to the selector unit 58 while being controlled by the input clock 52. A selector unit control signal 62 is supplied from the selector unit control register 92 to the selector unit 58, and the selector unit 58 outputs the output signal 56 from the pulse width generator 50 or “H” or based on the selector unit control signal 62. A flat signal of "L" level is output as the PWM output signal 64.

In the above structure, since the selector control register 92 is arranged in the data register 88 together with the input data register 90, the data register 88 reads the data 86 from the bus 78 once. The input data is stored in the input data register 90, and the selector control signal is stored in the selector control register 92. Therefore, the data register unit 88
Reads the data 86 from the bus 78 once,
The data register section 88 can supply the input data 54 to the pulse width generator 50 and the selector section control signal 62 to the selector section 58. Therefore, in the pulse width modulator, the selector control signal 62 can be used as a part of the data 86 like the input data 54, and the flat PWM output signal 64 from the “L” level to the “H” can be generated with a simple configuration. "Level flat PWM output signal 6
Up to 4 can be output arbitrarily.

Note that, in FIG. 4, the selector section control register 92 may be arranged above the most significant bit of the input data register 90.

[0040]

As described above, according to the present invention,
It is possible to arbitrarily output from a flat PWM output signal of “L” level to a flat PWM output signal of “H” level, and it is possible to improve the efficiency of D / A conversion in the pulse width modulation device.

[Brief description of drawings]

1 shows a pulse width modulator according to an embodiment of the present invention, FIG. 1A is a block circuit diagram thereof, and FIG.
It is a timing chart figure which shows the effect.

FIG. 2 is a block circuit diagram showing details of a pulse width modulator according to an embodiment of the present invention.

3A and 3B are block circuit diagrams of a pulse width modulator according to another embodiment of the present invention, where FIG. 3A shows a case where the selector unit includes an OR gate, and FIG. 3B shows a selector unit which includes an AND gate. Indicate the case.

FIG. 4 is a block circuit diagram showing a specific circuit configuration to which the pulse width modulator according to the embodiment of the present invention is applied.

FIG. 5 shows a conventional pulse width modulation device, (A) is a block circuit diagram thereof, and (B) is a timing chart diagram showing its operation.

FIG. 6 shows details of a conventional pulse width modulator, (A)
Is a block circuit diagram thereof, and (B) is a timing chart diagram showing its operation.

[Explanation of symbols]

 50 ... Pulse width generator 52 ... Input clock 54 ... Input data 56 ... Generator output signal 68 ... Selector section 60 ... "H" fixed signal 62 ... Selector section control signal 64 ... PWM output signal 88 ... Data register section 90 ... Input data register 92 ... Selector control register

Claims (3)

[Claims] 1. An input data register (90) for storing digital input data (54), and input data (5) from the input data register (90).
4), a pulse width generator (50) for outputting a pulse width modulated output signal (56), and a generator output signal (5) from the pulse width generator (50).
6) and a selector section (58) for receiving the selector section control signal (62), the selector section (58) is provided with a selector section control signal (6).
Based on 2), the generator output signal (56) or "H"
Alternatively, the pulse width modulation device is configured to output either one of the flat signals of "L" level. 2. The apparatus according to claim 1, further comprising a selector unit control register (92) for storing the selector unit control signal (62), the selector unit control register (9).
2) and the input data register (90) are arranged inside the data register unit (88). 3. The apparatus according to claim 2, wherein the selector unit control register (92) is arranged in the data register unit (88) together with the input data register (90), and stores the input data (54). At the same time, the pulse width modulation device is characterized in that the selector unit control signal (62) included in the data (86) from the bus (78) is stored.