JP2524165B2 - Signal side drive circuit of display device - Google Patents

Description

The present invention relates to a signal side driving circuit of a display device.

[Conventional technology]

Conventionally, in a signal side drive circuit of a display device provided with means for converting a digital video signal into serial-parallel conversion, the data bus is common to all bits and the digital video signal is always supplied to all sampling circuits.

[Problems to be solved by the invention]

However, in the conventional circuit, every time the digital video signal changes, all the loads attached to the data bus of each bit are charged and discharged, so that the more the number of outputs, the more the unnecessary current is consumed. was there.

The present invention solves the above-mentioned drawbacks of the conventional technique, divides the data bus into a plurality of blocks, and controls the time to supply a digital video signal, thereby reducing the consumption of the signal side drive circuit of the display device. The purpose is to measure current.

[Means for solving problems]

As means for solving the above-mentioned problems of the prior art, firstly, a video transmitted from a data bus according to a sampling pulse generating circuit and a sampling pulse sequentially output from the sampling pulse generating circuit. A signal side driving circuit of a display device, comprising: a data sampling circuit for sampling a signal, wherein the video signal is serial-parallel converted by the data sampling circuit, wherein the data sampling circuit is divided into a plurality of parts. Of the divided data sampling circuits, each of the divided data sampling circuits is provided with a corresponding buffer for inputting the video signal from the data bus and supplying it to the divided data sampling circuit. The generation circuit is arranged in the order of the plurality of divided data sampling circuits. The divided data sampling circuit that outputs the sampling pulse, supplies the video signal from the buffer corresponding to the divided data sampling circuit that outputs the sampling pulse, and outputs the sampling pulse to the divided data sampling circuit that does not output the sampling pulse. The video signal is not supplied from the corresponding buffer.

Secondly, in addition to the first configuration, the sampling pulse generation circuit receives the start pulse and sequentially outputs the sampling pulse to the first divided data sampling circuit, and subsequently, the second pulse. The sampling pulse is sequentially output to the divided data sampling circuit, and a timing signal is output in response to the output start of the sampling pulse to the second divided data sampling circuit, and in response to the start pulse. The video signal is supplied from the first buffer corresponding to the first divided data sampling circuit, and the video signal is supplied from the second buffer corresponding to the second divided data sampling circuit according to the timing signal. Is supplied.

[Action]

According to the present invention, by using the above-described means, the digital video signal is supplied to the data bus divided into some blocks by time control by itself.

Therefore, in the signal side drive circuit of the display device of the present invention, the digital video signal is supplied only to the blocks required for data sampling, thereby reducing the current consumption in the data sampling circuit and the buffer.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a case where a data bus is divided into two and a two-data sampling circuit array is time-controlled to supply a digital video signal in a signal side drive circuit of a display device according to the present invention. 1 is a buffer control circuit, to which a start pulse φ _S is input,
A buffer (A) control signal A and a buffer (B) control signal B are output. The buffer (A) control signal A is stored in the buffer (A) 2, and the buffer (B) control signal B is stored in the buffer (B) 3.
To the digital video signals D _{1 to} D ₄ , and the buffer (A) 2 is controlled by the buffer (A) control signal A to transfer the digital video signals D _{1 to} D ₄ to the digital video signals d _1A to d _4A as above buffer (B)
3 the buffer (B) control signal B to the control has been the digital video signal D ₁ to D ₄ of the digital video signal
and outputs as the d _1B to d _4B. Above digital video signal d _1A
.About.d _4A and the digital video signals d _{1B to} d _4B are input to the data sampling circuit array (A) 5 and the data sampling circuit array (B) 6 in the driver array 4, respectively. On the other hand, the sampling pulse generating circuit array 7 includes the start pulse φ _S and the clock pulse φ.
_C is input and the sampling pulses SP _{1 to} S are sequentially input.
P _N is output to the data sampling circuit array (A) 5 and sampling pulses SP _{N + 1 to} SP _2N are output to the data sampling circuit array (B) 6. In the data sampling circuit array (A) 5 and the data sampling circuit array (B) 6, the sampling pulses SP _{1 to} S ₁
The digital video signals d _{1A to} d _4A and the digital video signals d _{1B to} d _4B are sequentially sampled by P _2N . The sampled data is the latch pulse φ _L
Is sent to the brightness modulation circuit array 8 all at once by
The brightness is modulated and output from the output terminals SEG _{1 to} SEG _2N .
On the other hand, the sampling pulse generation circuit array 7 has the same timing pulse C as the sampling pulse SP _{N + 1} to the first stage of the data sampling circuit array (B) 6,
The sampling end pulse D is output to the buffer control circuit 1.

The operation of the signal side drive circuit of the display device of the present invention in the above configuration will be described with reference to FIG. Until the start pulse φ _S is input to the buffer control circuit 1, both the buffer (A) control signal A and the buffer (B) control signal B are the non-selection signal “L”, and the start pulse φ _S rises and the above The buffer (A) control signal A becomes the selection signal "H". By selecting the above buffer (A) 2,
The digital video signals d _{1A to} d _4A are output to the data sampling circuit array (A) 5 in the driver array 4. On the other hand, the sampling pulse generating circuit array 7 sequentially inputs the start pulse φ _S and the sampling pulses SP _{1 to} SP in synchronization with the falling edge of the clock pulse φ _C.
Output _2N . Among the sampling pulse SP ₁ to SP _2N, sampling pulses SP ₁ to SP _N is input to the data sampling circuit array (A) 5, the data sampling circuit array (A) 5 is the sampling pulse SP ₁ ~ At the falling edge of SP _N , the above digital video signal d _1A
~ D _4A is sampled. Further, among the sampling pulses SP _{1 to} SP _2N , the sampling pulses SP _{N + 1 to} SP _2N are input to the data sampling circuit array (B) 6 and have the same timing signal C as the sampling pulse SP _{N + 1.}
Is input to the buffer control circuit 1. The buffer control circuit 1 sets the buffer (B) control signal B to the selection signal “H” at the rising of the timing pulse C, and sets the buffer (A) control signal A to the non-selection signal at the falling of the timing pulse C. Set to “L”. The buffer (B) 3 is selected so that the digital video signals d _{1B to} d _4B are
By outputting to the data sampling circuit array (B) 6 in the driver array 4 and deselecting the buffer (A) 2, the output of the digital video signals d _{1A to} d _4A is stopped, and all the "H" signals are output. Or a constant code of "L" is output.

The data sampling circuit array (B) 6 samples the video signals d _{1B to} d _4B at the falling edges of the sampling pulses SP _{N + 1 to} SP _2N . The sampling pulse generating circuit 7 includes sampling pulses SP _{1 to} S of all stages.
When the output of P _2N ends, the sampling end signal D is output to the buffer control circuit 1. The buffer control circuit 1 sets the buffer (B) control signal B to a non-selection signal "L" at the fall of the sampling end signal D, and the buffer (B) is deselected to cause the digital video signal d to be deselected. stop _1B to d _4B output, to output a constant code of the all "H" or "L". Meanwhile, the data sampling circuit array (A) 5 and the data sampling circuit array (B)
The video data sampled in 6 is the latch pulse φ
_{When L} is input, the data is collectively sent to the brightness modulation circuit array 8 and subjected to brightness modulation and output from the output terminals SEG _{1 to} SEG _2N .

〔The invention's effect〕

As described above, according to the present invention, the following remarkable effects can be achieved.

a) In the data sampling circuit, since the sampling circuit is connected in parallel to the video signal supply line, the video signal is delayed for sampling at a position far away from the sampling pulse generating circuit. Although there will be a timing difference with the sampling pulse, since the video signal is supplied through the buffers provided in each, the timing deviation with the sampling pulse will occur even if sampling is performed at a position that is distant in distance. Can be prevented.

b) Since the data sampling circuit is divided, the load becomes smaller and the buffer circuit for supplying the video signal can be made smaller. Further, since the buffer circuit is made small and the buffer of the divided data sampling circuit which is not at the timing of data sampling does not supply the video signal, the current consumption in the buffer can be reduced. That is, the current consumption can be suppressed to one buffer having a small circuit, and the other buffer does not output the video signal and does not perform the buffer operation, so that the current consumption can be reduced.

c) The digital video signal is not supplied from the buffer to the divided blocks of the data sampling circuit which are not in the timing of data sampling, so that unnecessary current consumption due to charging / discharging in the blocks not in timing of data sampling is suppressed and the current consumption is reduced. it can.

d) Since the supply of the video signal to each of the divided data sampling circuits is automatically controlled by automatically switching the buffer according to the timing signal from the sampling pulse generating circuit, there is no need for an external switching signal, The operation is reliable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the embodiment. 1 ... Buffer control circuit 2 ... Buffer (A) 3 ... Buffer (B) 4 ... Driver array 5 ... Data sampling circuit array (A) 6 ... Data sampling circuit array (B) 7 ... Sampling pulse Generation circuit array 8 ... Luminance modulation circuit array

Claims (2)

(57) [Claims] 1. A sampling pulse generating circuit, and a data sampling circuit for sampling a video signal transmitted from a data bus according to sampling pulses sequentially output from the sampling pulse generating circuit. A signal side driving circuit of a display device, which is obtained by converting the video signal in series-parallel, wherein the data sampling circuit is divided into a plurality of divided data sampling circuits, and each divided data sampling circuit A buffer is provided corresponding to each of the divided data sampling circuits for inputting the video signal from the data bus to the circuit, and the sampling pulse generation circuit sequentially supplies the sampling pulses to the plurality of divided data sampling circuits. Is output from the sample A video signal is supplied from the buffer corresponding to the divided data sampling circuit that outputs a video pulse, and the video signal is output from the buffer corresponding to the divided data sampling circuit that does not output the sampling pulse. The signal side drive circuit of the display device characterized by not supplying. 2. A sampling pulse generating circuit, and a data sampling circuit for sampling a video signal transmitted from a data bus according to sampling pulses sequentially output from the sampling pulse generating circuit. A signal side driving circuit of a display device obtained by serial-parallel converting the digital video signal, wherein the data sampling circuit is divided into a plurality of divided data sampling circuits. The sampling circuit is provided with a buffer for inputting the video signal from the data bus and supplying the divided data sampling circuit to the divided data sampling circuit, and the sampling pulse generation circuit sequentially performs sampling for the plurality of divided data sampling circuits. Output a pulse, The video signal is supplied from the buffer corresponding to the divided data sampling circuit to which the sampling pulse is output, and the video signal is supplied from the buffer corresponding to the divided data sampling circuit to which the sampling pulse is not output. The sampling pulse generating circuit receives the start pulse and sequentially outputs the sampling pulse to the first divided data sampling circuit, and subsequently outputs the sampling pulse to the second divided data sampling circuit. And the timing signal is output in response to the start of the output of the sampling pulse to the second divided data sampling circuit, and the timing signal is output to the first divided data sampling circuit in response to the start pulse. Corresponding first said buff Is supplied from the video signal, and the second signal is supplied in accordance with the timing signal.
The signal side drive circuit of the display device, wherein the video signal is supplied from the second buffer corresponding to the divided data sampling circuit of.