JPH01261916A - Pulse width modulation circuit - Google Patents

Abstract

PURPOSE:To vary and average the power consumption timings of a circuit and to prevent the circuit from coming to a large noise source by shifting the phases of plural pulse width modulation output waveforms. CONSTITUTION:A basic timing signal S is selected or synthesized in accordance with data D1-D3 inputted to pulse width modulation/synthesis circuits 5-7, and pulse width modulation outputs PWM1-PWM3 are outputted. The output PWM1 is outputted to an external part as it is, and PWM2 and PWM3 are respectively outputted to the external part through delay circuits 8 and 9. Here, the output waveforms when data are all similar become identical as illustrated. With setting the delay time of the circuit 8 longer than the circuit 9, PWM1 which is not delayed, the output PWM2 which is delayed by a prescribed time and the output PWM3 which is delayed by the prescribed time much more come to have phase differences, and the rise and fall of respective waveforms are prevented from becoming coincident. Consequently, the temporary concentration of power consumption is prevented and the occurrence of noise can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation circuit having two or more pulse width modulation outputs.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional pulse width modulation circuit. When the original oscillation signal CLK is input to the basic timing generation circuit 1, the basic timing generation circuit 1 generates a basic timing signal S according to the weight of the number of bits of pulse width modulation.
are inputted to pulse width modulation synthesis circuits 5-7. Figure 5-5) are time charts showing the basic timing signal S when the number of bits of pulse width modulation is 4 bits, and each (4) is bit 4 (MSB, the bit weight is 2s ), (B) is bit 3 (bit weight 2”),
(C) is bit 2 (bit weight 21), and (b) is bit 1 (LSB, bit weight 20). Third
In the figure, data D1-D3 input from the outside are inputted to pulse width modulation synthesis circuits 5-7 via latches 2-4. The basic timing signal S is selected or synthesized according to the data D1 to D3 input to the Norculus width modulation synthesis circuits 5 to 1, and the pulse width modulation outputs PWM1 to PWM
WM3 is output.

For example, if the data D1 input from the latch 2 to the pulse width modulation synthesis circuit 5 is rlloIJ, bits 4 and 3 of the basic timing signal S, that is, FIG.
) and (B) are selected and synthesized, and the pulse width modulation output PWM1 shown in (g) of the same figure is generated by the pulse width modulation synthesis circuit 5.
is output from. Similarly, data D1 is rolloJ, r
If the data D1 is rolloJ, the basic timing signals S (see Figure 5) corresponding to each bit are selectively synthesized, and if the data D1 is rolloJ, the pulse width modulation output PWM1 is output as the pulse width modulated output PWM1. If the data D1 is r, 01.01j, the pulse width modulation output P
The waveform shown in (G) in the figure is output as WM1.

[Problem to be solved by the invention]

A conventional pulse width modulation circuit is configured as described above.
1 As shown in FIG. 3, multiple pulse width modulation outputs PWM1
~Assuming that all PWM3 data has the same content,
As shown in the time chart shown in FIG. 4C, the rising and falling timings of the waveforms of the pulse width modulated outputs PWM1 to PWM3 coincide. Then, the timing at which power is consumed in these pulse width modulation circuits 5 to 7 and their peripheral circuits coincides, and large noise is generated due to concentrated power consumption. It has the disadvantage of becoming a noise source. Furthermore, as the number of outputs from the pulse width modulation circuit increases, the power consumption increases, and this pulse width modulation circuit has become a large noise source.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce noise generated by pulse width modulation output in a pulse width modulation circuit, and to prevent noise from becoming a large noise source even if the number of outputs increases. The purpose is to obtain a pulse width modulation circuit that can prevent the above problems.

[Means to solve the problem]

The pulse width modulation circuit of the present invention has two or more pulse width modulation outputs, and the waveform phases of the pulse width modulation outputs are all different from each other, or only one of them is included.

[Effect]

In the pulse width modulation circuit of the present invention, by shifting the phases of a plurality of pulse width modulation output waveforms from each other, the timing of the power consumed by the pulse width modulation circuit is shifted, and the power consumption is averaged rather than concentrated at one time. to become

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the pulse width modulation circuit of the present invention, and the same reference numerals as in FIG. 3 indicate the same parts.
The explanation will be omitted.

The basic timing signal S is the pulse width modulation synthesis circuit 5 to 7.
The input data D1 to D3 are selected or combined, and pulse width modulated outputs PWM1 to PWM3 are output. Of these, PWM1 is output as is to the outside of the pulse width modulation circuit, and PWM2 and PWM3 are output to the outside of the pulse width modulation circuit via delay circuits 8 and 9, respectively.

Here, pulse width modulation outputs PWM1 to PWM3 when the data of pulse width modulation outputs PWM1 to PWM3 are all the same.
The time chart showing the waveform of PWM3 is shown in Figure 2 (
Shown in C'). If the delay time of the delay circuit 9 is set longer than that of the delay circuit 8, the pulse width modulation output PWM1 will not be delayed because it does not go through the delay circuit, and the output will be delayed for a certain period of time because it is output through the delay circuit 8. The pulse width modulated output PWM2 that is output via the delay circuit 9 and the pulse width modulated output waveform of the pulse width modulated output PWM3 that is further delayed by a certain period of time and outputted through the delay circuit 9 are all This means that they have a phase difference from each other. Therefore, the rising and falling timings of these three pulse width modulated output waveforms, that is, the timings at which the waveforms change, do not coincide. In other words, since the timings at which the respective pulse width modulation output waveforms change are shifted, the timings of the power consumed by the pulse width modulation circuit and its peripheral circuits are not concentrated at one time, thereby suppressing the generation of noise.

In this embodiment, the delay circuits 8 and 9 are inserted between the pulse width modulation synthesis circuits 6 and 7 and the output terminal to change the phase of the pulse width modulation output. The phase of the pulse width modulation output may be changed, or the phase of the basic timing signal S input to each pulse width modulation synthesis circuit 5 to 7 in the basic timing generation circuit 1 may be changed.

In addition, in this embodiment, all pulse width modulation outputs PW
Are the phases of M1 to PWM3 different from each other?
The phase of only a part of the pulse width modulation output may be changed.

The pulse width modulation circuit of the present invention may be used in a pulse width modulation circuit built into a microcomputer.

〔Effect of the invention〕

As described above, the pulse width modulation circuit of the present invention has two or more pulse width modulation outputs, and all or part of the phases of the pulse width modulation outputs are different, so that the pulse width modulation circuit outputs the pulse width modulation circuit. The timings at which the outputs change do not all coincide, and the power consumed by the pulse width modulation circuit and its peripheral circuits is not concentrated at once, making it possible to reduce the noise generated here. Furthermore, even if the number of outputs of this pulse width modulation circuit is increased, the power consumed by this circuit and its peripheral circuits is not concentrated all at once but is averaged out, making it possible to prevent an increase in the noise generated here. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart of the same embodiment, Fig. 3 is a block diagram showing a conventional example, Fig. 4 is a time chart of the conventional example, and Fig. 5. is a time chart showing basic timing signals and pulse (force-width modulation outputs). 1... basic timing generation circuit, 2 to 4...Φ latch, 5 to 7Φ... pulse width modulation synthesis circuit, 8,9・
轡...Delay circuit, CLK...Original oscillation signal, S...
・Basic timing signal, D1 to D3... Contention data, P
WM1 to PWM3...Pulse width modulation output.

Claims (1)

[Scope of Claims] A pulse width modulation circuit having two or more pulse width modulation outputs, wherein the phases of the waveforms of the two or more pulse width modulation outputs are completely different or partially different. .