SU1485217A1 - Multiphase pulse stabilizer - Google Patents

Description

The invention relates to sources of secondary electrical and electronic equipment. The invention relates to sources of secondary electrical and electronic equipment.

The aim of the invention is to improve the technical and economic indicators and enhanced functionality.

Figure 1 shows the scheme of a multiphase pulse stabilizer ^ 'in figure 2 and 3 - voltage diagrams ^' in figure 4 - typical dependencies between the level of ripple on the output, the number of phases and the fill factor,

2

paratura. The invention contributes to the improvement of technical and economic indicators and expanding the functionality of multiphase pulse stabilizers by providing the ability to automatically change the number of phases depending on the fill factor in the operating mode. The essence of the invention is that a multiphase pulse stabilizer containing a power circuit made in the form of M parallel-connected converter cells and a control unit are entered into a memory register and a code converter, with the inputs of the register bits connected to the outputs of the first clock pulse generator , K-bit binary counter and the coding inputs of the digital comparison circuit, the register outputs are connected to the inputs of the code converter, the outputs of which are connected to the digital coding inputs oh comparison schemes. 4 il.

The stabilizer contains a power source 1 connected to the power converter cells 2, the output terminals of which are connected to the load 3 in parallel, and the control unit 4. The control unit contains a generator of 5 sync pulses, the first 6 and the second.

7 drivers of clock pulses, the first 8 and second 9 drivers of strobe pulses, driver of 10 pulses of synchronization of a pulse-width modulator 11, universal M-bit register 12, M-bit shift register 13, source

,, ЗЦ „„ 1485217

3

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four

14 reference voltage, analogue comparison node 15, M logic elements 16, M control triggers 17, control unit power supply 18, K-bit binary counter 19, K-bit digital comparison node 20, coding unit 21, memory register 22, converter 23 codes.

The voltage plots of FIG. 2 are shown in: o - output of the first driver of 6 clock pulses; $ - output shaper 10 synchronization pulses of the pulse-width modulator; & - output pulse-width modulator 11; £ - first exit

the discharge of the M-discharge register 13 shift; - the output of the second digit of the M-ray register 13 shift; e - the output of the M-th digit of the M-bit register 13 shift; W - the output of the second strobe pulse shaper 9, the y - output of the second shaper 7 clock pulses, C - the output of the first register bit 12; to - the output of the second digit of the register 12; L output of the M-th digit of the register 12, the 'M output of the first shaper 8 strobe; to the output of the first control trigger 17; On the output of the second trigger 17 control; and - the output of the M-th control trigger 17, p - the output of the digital comparison node 20.

The voltage plots of FIG. 3 are shown in: a - output of the first driver of 6 clock pulses; 5 "- the output of the first discharge of the K-bit binary counter 19; |> - the output of the second discharge of the counter 19; -2 - the output of the third discharge of the counter 19; - the output of the digital comparison node 20; e the output of the former 10 synchronization pulses of the pulse-width modulator;> to - the output of the shaper 6 clock-pulses; - the output of the second discharge of the counter 19, "and - the output of the third discharge of the counter 19;

To - the output of the third discharge of the counter 19; l - the output of the digital node 20 comparison; m - the output of the driver pulse synchronization pulse-width modulator 10.

Figure 4 shows the dependence of the variable component of the output voltage of the stabilizer on the fill factor and the number of power channels.

Power supply 1 and power channels 2 have two common buses. The load 3 in the case of galvanic isolation does not have a common connection point with the power source 1. The generator 5 sync pulses output connected to the shapers 6 and 7 clock pulses. The output of the first driver 6 clock pulses connected to the input of the K-bit binary counter 19, to the first driver 8 strobe pulses, to the clock input of the M-bit register 13 shift. One of the inputs of the pulse-width modulator 11 is connected to the output of the synchronization pulse generator 10, and the other is connected to the output of the analog comparison node 15, one of the inputs of which is connected to the voltage source 14 and the other to the load 3. The output of the pulse-width modulator 11 is connected to the input of the second driver of the 9 strobe pulses and to the information input of the M-bit register 13 shift. The output of the second gate driver 9 strobe pulses is connected to the input selection input mode of the universal M-bit register 12, to its synchronization input of the parallel receive mode information and to the information input of the serial receive information, as well as to the installation input to the "0" of the second imaging unit 7 clock pulses. The output of the driver 7 is connected to the synchronization input of the serial mode of receiving information of the universal M-bit register 12. The input of the first discharge of the universal M-bit register 12 is connected directly or through a resistor to the positive bus of the control unit power supply 18, the rest (M-1) inputs from the second on M th connected to the negative bus power source 18. The outputs of the first, second, ..., M-th bits of the register 12 are connected to the synchronization inputs of the first, second, ..., M-th triggers 17, and the outputs of the first, second, ..., ..., M- th bits of the universal register 13 shift connected to the second inputs of the first, second, ..., M-th logic element 2I-NOT 16, the other inputs of which are connected to the output of the driver 8 strobe pulses. The output of the first, second, ..., M-th logic element.2I-NOT 16 is connected respectively1

to the input K of the first, second, M-th control trigger 17,

the output of which is connected to the input of the first, second, ..., ..., Mth power channel 2, respectively, and the непосредственноinput or resistor directly to the positive bus of power supply 18, the outputs of the first, second, ..., K- second bits of the binary counter 19 are connected to the information inputs of the first, second, ..., K-th bits of the digital comparison node 20, respectively. The outputs of the first, second, ..., K — th bits of the coding unit 21 are connected to the coding inputs of the first, second, ..., K — th bits of the digital comparison node 20, respectively, (K + 1), the output of the coding block is connected to input control state of the outputs of predvoddl'elya 23 codes. The output of the digital node, 20 comparison is connected to the input K. installation in the "0" K-bit counter 19 'and to the input of the shaper 10 synchronization pulses of the pulse-width modulator. The storage register 22 inputs of the first, second, ..., η-th bits are connected to the outputs of the corresponding bits of the first driver 6 clock pulses, inputs (n + 1), (n + 2), ..., (n + K) first digits - with the first, second, K-m output discharge of the counter 19, and the inputs (n + K + 1) -th, (n + K + 2) -th, ..., (n + + 2K) ~ th discharge - with the first, second, ..., K-mi output bits of the Converter 23 codes and the input bits of the digital circuit 20 of the comparison. The synchronization input register 22 is connected to the output of the second driver 9 strobe pulses. As a power conversion cell 2, single-cycle and push-pull converters operating in switching mode can be used, made according to any of the known schemes. Binary η-bit counters (for example, type K 155IE5) can be used as drivers of 6 and 7 clock pulses, and permanent (reprogrammable) memories (for example, type K573РФ2) can be used as a converter of 23 codes. All cascades of the control unit 4 are powered from the power source 18.

1485217

Multiphase pulse stabilization ··· torus works as follows.

From the generator output 5 clock pulses voltage with a period

. t _gn = 0.01 τ · κ ,,

where T is the switching period of power

channels - converting cells 2 ·,

- the required fidelity of the pulse duration of the output signal of the pulse-width modulator 11 at the input of the power converter cells 2, X,

enters the input of the formers of 6 and 7 clock pulses. At the same time, the item will be determined from the expression

η = 1 Ou l (tm - ^ -), (1)

where M is the maximum possible number of power converting cells 2 (ha is the number of working power converting cells 2).

Output Voltage Formers

6 and 7 clock pulses, shown 3θ, respectively, on plots a, (figure 2),

in general, they may have a phase shift. Their period Τ _η = Τ / πι determines the required time shift between the electrical processes in the power

35 conversion cells 2. A sawtooth voltage and _n (b) with a period T (FIG. 2, b) at the output of the shaper 10 and a constant voltage and _ss (b) at the output of the comparison unit 15 are used to form at the output of the modulator 11 a width-modulated signal with a pulse duration of b _c and a period T (figure 2, c). The specified signal is fed to the information input of the register 13 shift. Za4

Writing information by the shift register 13 is carried out by a slice - by reheating 1/0 - clock pulses (figure 2, a), coming from the output of the driver

5θ 6 to the input of the synchronization register 13. This ensures that the register 13 has a high voltage level at the output of the first discharge at time 6 = 0 · (figure 2, d) and at the output of the M-th discharge at time b = (M-1) T ₍₎ . In general

55 the pulse duration at the output of the register 13 (figure 2, d-e) differs from the duration of the pulses at the output of the pulse-width modulator 11

7

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(FIG. 2, c) by the value of О ^ й С £ · _η · Such an error is also present in the prototype. The simultaneous presence of high levels at the inputs of logic elements 2I-NOT 16 ensures that at the inputs K. the control flip-flops 17 are at a low level and are set to “O ·”. According to the time diagrams of voltages at the input of logic elements (FIG. 2, d-f) at the output <3 of the first trigger 17, a high level appears at the time ϋ = 0, at the output of the second trigger 17 - at the time C = T _p , at the output M first trigger 17 - at the moment ύ =

= (M-1) T _p . Up to the moment C = universal M-bit register 12

is in the mode of sequential reception of information with a shift to the right, since at the input of the selection of the information mode there is a low level (figure 2, g). Clock pulses from the output of the imaging unit 7 (Fig. 2, g) are fed to the synchronization input of the register 12 and provide with a slice - a difference of 1/0 - the recording of the input to the information input of a low level.

At time b = Sc (figure 2, c) at the output of a pulse-width modulator, a low voltage level is formed. In a slice - difference 1/0 of this signal, the driver 9 provides a short strobe pulse (FIG. 2, g), which sets the driver (counter) 7 at input K to “0” with a high level, and register 12 to the parallel receiving mode . Since the input of the first digit is connected to the positive bus of the power supply source 18, and the inputs from the second to the M th digit are connected to the negative bus of the power supply 18, then at the time of the 1/0 strobe pulse, a high level is recorded in the first digit of the register 12, and low level - in other categories. After the end of the strobe pulse, the driver (counter) 7 provides pulses with a period of T _y (starting from b = C) at the synchronization input of the register 12, which has switched to the sequential receiving mode. The high level recorded at time C = b _{c will} remain at the output of the first digit of register 12 in the interval P _c <P <Pc + T _b (FIG. 2, i) Next, the operation of register 12 in the shift mode is illustrated in FIG. 2k, l. Thus, in the register 12, a high voltage level will appear with a day time T _p at the output of the first discharge at time b = b ^ at the output of the second discharge at time C = C _c + T _p , at the output of the M-th discharge at time b = b _c + (M-1) T _and . Since the outputs of the digits of the register 12 are connected to the synchronization inputs of the control trigger 17, then at the indicated times the front (1/1 switching of the trigger 17 takes place (since the уровень-input is high). Shapes 6 and 7 have the same bit depth. This ensures the formation clock pulses with the same period Τ _ή , but with a phase shift, since the initial state of the driver (counter) 7 is synchronized at the moment of time b _C. As a result, at the output of the control trigger 17 we get the width-modulated 2 pulses (Fig.2, n, n, o), equal in duration to the signal at the output of the pulse-width modulator 11. Their time shift by an amount ensures the time shift of the electrical processes in the power converter cells 2. In the following periods of time, the processes are repeated in the same way Thus, the multiphase pulse stabilizer according to the scheme of FIG. 1 operates when code 00 ... 00 is fed from the coding unit 21 to the digital comparison node and the outputs of the code converter 23 are set to a high impedance state with (К + 1) ~ th output to diruyuschego unit 21. In this case, the maximum number of used cells converting M, K-bit binary counter 19 is set to 00 ... 00 in a natural way in the calculation process, the register 22 and the code converter 23 to work the whole circuit have no effect.

The number of bits of the binary counter 19 and the digital comparison node 20 is determined by the maximum possible number M of power channels 2 and is determined by the expression

1 + 1о§ ₂ (M + 1) 5 1о§ (M + 1),

K = 1, 2, 3 ... (2)

Output signals on each of K

the outputs of the coding block 21 can

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take two values: "O" - low voltage level "1" - high voltage level. Suppose that at the output of the first three low-order bits of the coding block 21, high voltage levels are set, and from the fourth to K-th (with K »3) - low levels. This means that the output of the coding block 21 is set to a binary number 111, corresponding to the number 7 in the decimal number system.

In this case, at the input of the digital comparison node 20, a signal will appear (high voltage level) only in the case 15, when the output of all three low-order bits of the K-bit counter 19 will simultaneously contain high voltage levels. This happens at times C _o , ϋ ₄ , 20

C (fig.Z, a-d) at equal time intervals T = 7 T „. A high voltage level from the output of the digital comparison node 20 arrives at the indicated times at input 25

installation in the "0" K-bit counter 19 and to the input of the driver 10 sawtooth voltage This signal provides installation in the "0" counter 19 (Fig.Z, a-g) and the drop in peak-30 voltage at the output of the imaging unit 10 (Fig. 3, e). On FIG. 3, the case is shown when the binary number 1100 is set at the output of the coding block (12 in the decimal system). When this reset to "0" of the counter 19 and the synchronization of the driver 10 is performed at time points,

C, (fig.Z, k, l) at equal time intervals T = 12 "T. Thus, the installation of the binary number w comparison at the inputs of the digital node 20 makes it possible to form the period of the sawtooth voltage T, which is W times the repetition period of such 45 pulses. This makes it possible to form uniformly shifted identical signals for controlling the power transformer phases (the case where __

ha = M).

Figure 4 shows the dependences of the relative values of the amplitude of the first harmonic of the pulsations in the output voltage for a different number. For example, when the value of the fill factor K is less pulsation, a circuit with four phases gives, with a circuit with five phases. These

dependencies should be used to select the number of phases both when designing converters with a fixed number of converter cells, and when setting the number of power channels in the proposed system or in the prototype. For operation in the mode of automatic selection of the number of phases, the coding unit 21 is set to the position when the signal from its (K + 1) ~ th output transfers the converter outputs 23 codes from the high-impedance state to the working state, while the outputs of the coding unit 21 connected to the digital node inputs 20 comparisons, go into a high-impedance state.

At the moment of equality of the voltage sweep and voltage from the node 15, the second driver 9 supplies a strobe pulse to the synchronization input of the memory register 22 (FIG. 2, g). The ratio of the number of pulses from the generator is 5 sync pulses transmitted to counters 6 and 19 before the moment of arrival of the pulse from the driver 9 to the number of pulses that fit in period T is nothing but the fill factor (Fig.2, b, c). This means that the strobe-pulse from the driver 9 writes to the register 22 a binary number proportional to the fill factor. Determine the digit capacity of the register 22. Counters 6 and 19 are together (K + n) bits. Pulse number

ows on period T varies depending on the working number of converter cells ha, therefore, in order to uniquely determine the fill factor according to the state of counters 6 and 19 for any w, it is necessary to introduce K additional bits. Information is sent to these bits either from the existing outputs of the coding block 21 (in the case of a non-automatic workstation, manually setting the number of working power channels 2), or from the corresponding outputs of the converter 23 codes (in the case of automatic selection of the number of power channels 2). Total register 22 must have (2K + n) digits. Each binary (2K + n) bit number has its own fill factor value and its own ripple-optimal number of power channels, determined from the curves in FIG. 4. Converter 23 codes for each sign 1485217 1 2

The output (2K + n) of a bit binary number received at its input gives out a K-bit binary number at the output, setting through digital comparison node 20 the number of power channels ’sh minimizing output pulsations. According to the same algorithm, the persistent storage device works, if we consider (2K + n) the inputs of block 23 as the address bus, and K its outputs as the data bus.

Example. Consider the case when a multiphase pulsed voltage stabilizer with the maximum number of power channels M = 5 and the number of pulses of the generator output voltage is 5 sync pulses on the period T following the width-modulated 20 signal of the driver 10, equal to 1000, i.e. T / T _um = 1000. Therefore, taking into account (1) and (2), the widths η for drivers 6 and 7 and K for binary counter 19 and coding block 25 21 must satisfy

n> 1о§ ₂ (---) = 1о§ ₂ (——) = 8,

* TCs ’->

TO? 1 ₂ (M + 1) = 3. thirty

Taking into account η = 8 and K = 3, the width of the storage register 22 should be n + 2K = 8 + 2 3 = 14, and the 23 code converter should represent a storage device storing K = 3 bit binary number in P addresses

, t · m; = g gi

40

Indeed, in a multiphase pulse stabilizer, information about the operation mode may change with the arrival of each pulse, therefore, when a multiphase pulse stabilizer is operating with the maximum possible M = 5 power channels 2, you must have: for ί = 5 1000 addresses (since T / T _gi =

= 1000) ·, for ί = 4,800 addresses (since T / T _gi = 800); for ϊ = 3600 addresses (since T / T _{g (=} 600) for ί = = 2400 addresses (since T / T _w = 400).

Thus, to select the operating mode of a multiphase pulse stabilizer with either two or three, ..., or five power channels 2, you must have information stored in the P addresses

equal to 1000 + 800 + 600 + 400 = = 2800.

Taking into account that the output information of the converter of 23 codes is characterized by three digits, then in this example the organization of memory 3 x 2800 is required.

Note that at the time of passage of the strobe pulse from the shaper 9, the number of pulses K. from the beginning of the period in counters 6 and 19 is proportional to K ^. Since in the period * G with different numbers of power channels 2, a different number of pulses of the clock generator fits, then the same fill factor corresponds to different fill factors.

For example, let the strobe-pulse at the output of the shaper 9 recorded that in the counters 6 and 19 at this moment of time contains the binary number 100, i.e. At the beginning of the period one hundred impulses passed. If the multiphase pulse stabilizer functions with five power channels 2ί = 5 and in the period T there are 1000 pulses of the output voltage of the generator 5 sync pulses, then Κι = 100/1000 = = 0.1, if ΐ = 4, then K, = 100/800 = = 0.125, etc.

To determine, it is necessary to know not only the number of pulses K transmitted to counters 6 and 19 from the beginning of the period up to the strobe-pulse period from shaper 9, but also the number of pulses in period T characterizing the number of functioning power channels 2. This information is located at the transducer outputs 23 codes in the form of K-bit binary words (in this case K = 3).

Now let us consider which codes are written in the constant memory cells of the converter of 23 codes. Let us denote binary numbers corresponding to the contents of counters 6 and 19 at the output of the converter of 23 codes at time p. the appearance at the output of the imaging unit 9, respectively, as A _e1x6 (6;) and a _watts . _r3 (b;). Thus, at the outputs of the storage register 22 at the moment of time after passing to its output, the syn13

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the strobe pulse from shaper 9 will be recorded code

^A vyh.6, Yu ^L Ekl "1E · Define using graphs 4, which number must be written at this address in the transmitter 23 codes. Let A be you * 6, <9 (* · <) ~ 100, and A _{bb | Y 2F} (c ₄ ) = 5. This corresponds = 0.1. From figure 4 it follows that the smallest variable component will be in the case of working with five power channels 2, therefore in the cell corresponding to the address ^A YO * ^L out-2} ( ^e <)> should be

The number 5 is written. Let at the time moment b ^ the appearance of a strobe pulse at the output of the shaper 9 we have ^A output units? ⁼ 250 and L, „-23 (1: ι) = 5. This corresponds to K. = 0.25 = _250/1000 .

From the graphs of Fig. 4, it follows that for a fill factor of 0.25, a smaller value of the variable component of the output voltage corresponds to operation with four power channels, therefore, there are 23 codes with the address A _ve in the converter cell _(X (b ₂ ) = 250 and A _{6b) X} (b _g ) = 5 should be written the number 4.

The programming of the contents of all cells of the code converter 23 is performed with regard to the graphs of FIG. 4. For example, programming is performed at the beginning for А _{ВЬ | Х23} = 5 and А _{0Ь1Х ел9} from 1, 2, 3, ..., 1000, then for

^And you ”73 ^{= A and A} output 6.1? ^from 1 ”2, 3, ...,

..., 800, etc.

At time b; the arrival of the strobe from the driver 9 to the synchronization input of the register 22 At its information inputs there are codes А _ВЬ1Хбл , (b _; ) and A _out "(b; _,),

where ^L 8SHI 22 ~ previous ^code

work period corresponding to the point in time b. This is because the operation of the coding unit 23 does not occur instantaneously, i.e. when recording into register 22 a code A _{6b (Hb19} (B ·) A _{V rs} wk (£;) code converter 23, the output code does not have time to change and A corresponds to _{BL (X23} (b,

I

The advantage of the invention in comparison with the prototype is the increase of technical and economic indicators, expansion of functionality by providing the ability to automatically change the number of phases depending on the fill factor in the operating mode. This allows an average decrease of 20-30%

ripple output voltage or the same amount to reduce the inductance of smoothing chokes in the power converter cells. Technical and economic displays and powered equipment increase (the volume and mass of smoothing filters decrease, reliability increases).

Claims (1)

Claim Multiphase pulse voltage regulator containing a power circuit made in the form of M parallel-connected power channels, each of which is connected to input and output terminals, and a control unit consisting of a clock generator, a synchronization pulse shaper, a pulse-width modulator, an M-bit register shift, universal shift register, control M-flip-flops, 2I-NE Mlogical elements, two clock pulse shapers, two strobe pulse shapers, a reference source for voltage, analog comparison node, {(-digit binary counter, {(-digit digital comparison node, coding block and power supply of the control unit; an analog comparison node with one of the inputs connected to the reference voltage source, the other to the output terminals, and output - to one of the inputs of the pulse-width modulator, the other input of which is connected to the output of the synchronization pulse shaper of the pulse-width modulator, the output of the pulse-width modulator is connected to the information input of the M-digit The second shift register and through the second strobe pulse shaper - to the inputs of the universal .M-bit register and to the installation input to "0" of the second clock generator, whose output is connected to the synchronization input of the serial mode information of the universal M-bit register, and input - to the output of the clock generator and the input of the first driver of clock pulses, each output of the universal M-bit register is connected to the input, the synchronization of the corresponding control trigger, to the output m which 15 • 1485217 1 6 The control inputs of the power channels are connected, for a K-bit counter, the input is connected to the output of the first driver of clock pulses, each of the K-outputs is connected to the corresponding information inputs of a digital comparison node, in which the coding is connected to the corresponding outputs of the coding unit, and the output to the installation input in the "About" K-bit binary counter, the input of the driver of the synchronization pulses of the pulse-width modulator, the output of the first driver of the clock pulses is connected to the input of the M-bit shift the register and through the first driver strobe pulses to the first inputs of M logic elements 2I-NOT, the input of the first discharge of the universal M-bit register is connected directly or through a resistor to the plus bus of the control unit power supply, the rest (M-1) inputs are from the second to M th connected to the negative power supply bus, the outputs of the first, second, ..., ..., M-th bits of the M-bit shift register connected to the second inputs of the first, second, ..., M-th logical element 2I -NO, exit the first, second, ... ..., M-th logs eskogo 2I-NO element is connected respectively to an input of first, second, ..., Mth trigger control of aphids sistent the fact that, in order to improve technical and economic indicators, expand the functionality of multiphase pulse stabilizers by providing the ability to automatically change the number of phases depending on the fill factor in the operating mode, a memory register and a code converter are entered, while the memory register has inputs of the first, second, ..., ..., η-th bits are connected respectively to the outputs of the first, second, ..., η-th digit of the first driver of clock pulses, inputs (n + 1), (n + 2), ..., (n + K ) th register bits are connected respectively to the outputs of the first, second, ..., K-th bits of a K-bit binary counter, the inputs (n + K + 1), ..., (n + 2K) bits are connected respectively to the inputs of the first, second, ..., K-th digit of the digital comparison node, the synchronization input is connected to the output of the second strobe pulse shaper, and the outputs of the first, second, ..., (n + 2K) -th digits are connected to the corresponding vuyuschimi input code converter, which outputs the first, second, K-th bits are connected to respective inputs of encoding digital comparison unit, and outputs the state control input connected to the output (K + 1) -th bit of the encoding unit. 1485217 FIG. 2 1485217