SU1070528A1 - Polyphase pulse stabilizer - Google Patents

Abstract

MULTI-PHASE. PULSE voltage stabilizer containing a power circuit made in the form of parallel-connected power converter cells, each of which is connected to the input and output pins, and a control unit consisting of a synchro-pulse generator that generates a sync pulse of a pulse-width modulus torus, M-bit shift register, universal shift register, control m triggers, NAND logic gates, two clock pulse shapers, two gate-pulse shapers the reference voltage source, the analog reference node, the analog comparison node being connected to one of the inputs to the reference voltage source, the other to the output terminals, and the output to one of the inputs of the pulse-width modulator, the other input of which is connected to the output the synchronization pulse generator of the pulse width modulator, the output of the pulse width modulator is connected to the information input of the M-bit shift register and through the second gate generator to the inputs of the universal M - of the bit register and to the input of the second clock generator in O, the output of which is connected to the synchronization input of the serial mode of receiving information from the universal I-bit register, and the input to the output of the clock generator and to the input of the first clock shaper, the input of the synchronizing pulse generator the pulse-width modulator is connected to the synchronization input of the M-bit shift register and (g through the first gate generator (L pulses to the inputs M of logic elements NON, each output of the universal M-bit register is connected to the synchronization input of the corresponding control trigger, the outputs of which are connected to the control inputs of the power converter cells, characterized in that, in order to increase the functional- capabilities, a binary digit counter, a digital bit comparison node and a modulating block are introduced, the input (the "bit discharge counter is connected to the output of the first clock clock oo pulses, and each of the outputs to the corresponding information The inputs of the digital node are comparable, the coding of the inputs of which are connected to the corresponding outputs of the coding block, and the output - to the input of the installation in O to-bit binary counter and the input of the synchronization pulse generator of the pulse-width modulus ra.

Description

The invention relates to electrical engineering and can be used as sources of electrical power for electrical and radio electronic equipment. A multiphase pulse voltage regulator is known, which contains a power circuit made in the form of M parallel-connected power converter cells, each of which can be carried out using any of the known circuits for converting electrical energy, and a control unit consisting of a sync pulse generator synchronization pulses of the pulse-width modulator, M-bit shift register, reference voltage source, analogue comparison circuit Hz. The disadvantage of this stabilizer is low reliability and low specific mass indicators due to the fact that the current distribution is evenly distributed between parallel-working power converter cells as the number M of parallel-connected power cells increases. In addition, the control unit only provides control of a fixed number of converter cells. This eliminates the use of the same control unit when the number of converter cells changes and requires the development of a new control unit. Closest to the proposed technical entity is a multiphase pulse voltage regulator containing a power circuit made in the form of an M parallel to the included power converter cells, each of which is connected to the input and output power terminals, and a control unit consisting of a sync generator pulses, pulse generator of synchronization of a pulse width modulator M-razravnyh shift register, universal shift register, M control triggers, I-NE logic elements, two pho , worlds of clock pulses, two gate formers of strobe pulses, reference voltage source, analogue comparison node, the comparison node with one of the inputs connected to the reference voltage source, the other to the output pins of the stabilizer, and the output to the same from the inputs of the pulse-width modulator, the other output of which is connected to the synchronization pulse shaper of the pulse-width modulator, the output of the pulse-width modulator is connected to the information input of the M-bit shift register and through the second the strobe pulse driver to the inputs of the universal M bit register and the setup input to the second clock pulse generator, the output of the synchronization pulse generator of the pulse width modulator is connected to the synchronization input of the serial mode of receiving information of the universal M-bit register, and the input to the pulse generator and the input of the first clock pulse generator, the output of which is connected to the synchronization input of the M-bit shift register and through the first gate-pulse generator in to the inputs M of the NAND logic elements, each output of the universal M-bit register is connected to the synchronization input of the corresponding control trigger, to the outputs of which the control inputs of the power conversion cells C2 are connected. A disadvantage of the known stabilizer is the limited functionality and low efficiency due to that the stabilizer is not working when the number of converter cells is changed without additional development and manufacturing costs. designed multiphase device. The purpose of the invention is to expand the functionality. The goal is achieved by the fact that in a MULTIPLE PHASE voltage regulator / containing a power circuit, made in the form of M parallel-connected power converter cells, each of which is connected to the input and output power terminals, and the control unit, which is separate from the clock generator , synchronization pulse generator of a pulse width modulator, M-bit shift register, universal shift register, M control triggers, M NAND logic elements, two clock shapers pulses, strobe pulses double formers, a reference voltage source, an analog reference node, the comparison node with one of the inputs connected to a voltage source, the other to the stabilizer output pins, and the output to one of the inputs of a pulse width modulator, another input of which is connected to the output of the synchronization pulse generator of the pulse-width modulator, the output of the pulse-width modulator is connected to the information input of the M-bit shift register and through the second driver strobe pulses - to the inputs of the universal M-bit register and to the input of the second O-clock generator in the O device, the output of which is connected to the synchronization input of the serial mode of receiving information of the universal M-bit register, and the input to the clock generator and: of the first shaper clock pulse input, the synch pulse pulse shaper pulse modulator input is connected to the Synchronization input of the M-bit shift register and through the first strobe pulse shaper - to the inputs M of the logical elements NAND, each output of the universal M-bit register is connected to the synchronization input of the corresponding control trigger, to the outputs of which are connected the control inputs of the power conversion cells, a K-bit binary counter, a K-bit digital comparison node are entered and a coding unit, the input of the K-bit counter being connected to the output of the first clock clock generator, each of the K outputs to the corresponding information inputs of the digital comparison node, the coding inputs of which th connected to respective outputs of the encoding unit and output to the set input of G K-bit binary counter and an input of the synchronization pulses of the pulse width modulator.

FIG. 1 is a diagram of a multi-phase imp / low stabilizer; 2 and 3 are stress plot.

The stabilizer contains a power source 1 connected to the power converter cells 2, the output terminals of which are connected to the load 3 in parallel or in series, the control unit 4. The control unit contains a generator of 5 sync pulses, the first b and second 7 drivers of clock pulses, the first 8 and second 9 drivers of strobe pulses, the driver 10. Synchronization pulses, a pulse width modulator 11, a universal M-discharge register 12, and a discharge register 13, a source 1; 3 of the reference voltage; a node 15 of the voltage; and logic elements 16,. And the control flip-flops 17, a power source 18 of the control unit, a K-bit binary counter 19, a reference comparison node 20, an encoding unit 21.

Power supply 1 and power conversion cells 2 have

two common tires. The load 3 in the case of galvanic isolation does not have a common connection point with the power source 1. A generator of 5 sync pulses is connected to the output of b and 7 clock pulses. The output of the first clock pulse generator b is connected to the input of the K-bit binary counter 19, to the first gate generator 8, to the synchronization input of the M-bit shift register 13. One of the inputs of the pulse-width modulator 11 is connected to the output of the Shaper 10 of the synchronization pulses, and the other to the output of the analog reference node 15, one of the inputs of which is connected to the source 14 of the reference voltage, and the other to the load 3. The input of the pulse-pulse the modulator 11 is connected to the input of the second strobe pulse generator 9 and to the information input of the M-bit shift register 13. The output of the second strobe pulse generator 9 is connected to the input selection mode input information of the universal m-bit register 12 and to its synchronization input of the parallel receive mode information and to the information input of the serial receive information, as well as to the installation input of the second shaper 7 clock pulses . The output of the imaging device .7 is connected to the synchronization input of the serial mode of receiving information,) of the universal.-Bit register 12. The input of the first digit of the universal M-bit register 12 is connected directly or I. through the resistor to the plus bus of the control unit power supply source 18, the remaining (M-1) inputs from the second terminal are connected to the negative bus source liB of the power supply. The outputs of the first, second, ..., M th register bits 12 are connected to the synchronization inputs of the first, second, ..., M th trigger 17, and the outputs of the first, second, ..., M th bits the register 13 is connected to the inputs of the first, second, ..., M th logical element AND-NOT 16, the other inputs of which are connected to the output of the strobe pulse generator 8, the output of the first, second, ..., M th logical element NAND., 16 are connected respectively to the input C of the first, second, ..., control trigger 17, the outputs of which are connected respectively to the input m of the first, second, .., M-and power converter cells 2, and L-in moves directly or through a resistor - jf. The positive mine of the power source 18, the outputs of the first, second, ..., Kth bits of the binary counter 19 are connected to the information inputs of the first, second, .., Kth bits of the digital comparison node 20, respectively. The outputs of the first, second ..., K-th bits of the coding unit 21 are connected to the coding inputs of the first, second, ..., K-th bits of the digital comparison node 20, respectively. The output of the digital comparator node 20 is connected to the input Q of the installation in the O-K-bit of the counter 19 and to the input of the driver 10 of the synchronization pulses of the pulse-width modulator. Single-cycle and two-stroke converters operating in the switching mode, made according to any known scheme, can be used as a power converter cell 2. Binary counters can be used to form hoists of 6 and 7 clock pulses. All cascades of the control unit 4 {5,6, ..., 17,19, ... 21) are powered from the power source 18. The voltage plots (Fig. 2) are shown: 22 — at the output of the first shaper of clock pulses; 23 at the output of the shaper 10; pulse synchronization of a pulse-width modulator; 24 — at the output of a pulse-width modulator 11; 25 — at the output of the first digit M -rush register 13 shift, 26 - at you during the second discharge of the M-discharge register 13 shift, 27 - at the output of the M-th digit of the M-discharge register 1 3 shift, 28 - at the output of the second driver 9 strobe pulses , 29 - at the output of the second shaper 7 clock pulses, 30 at the output of the first discharge un Versal M-bit register 12, 31- output. The second bit of the universal M-bit register 32- at the output of the Mth bit of the universal M-bit register 33- at the output of the first gate stator 8, 34 - At the output of the first control trigger 17, 35 — at the output of the second control trigger 17, 36 — at the output of the control trigger 17, 37 — at the output of the digital comparison unit 20 The voltage plots (FIG. 3) show: 38 —the output of the first generator 6 clocks pulses, 39 at the output of the first bit of a K-bit binary counter 19, 40 on output of the second bit of the K-bit of the binary counter 19, 41 — at the output of the third bit of the K-discharge of the binary counter 19, 42 — at the output of the digital comparison node 20, 43 — at the output of the former 10 and the synchronization pulses of the pulse-width modulator, 44 - during the generator 6 clock pulses, 45 - at the output of the second discharge of the K-discharge binary counter 19, 46 - at the output of the third discharge of the K-discharge binary counter 19, 47 - at the output of the fourth discharge of the K-discharge binary counter 19, 48 - on the digital node 20 of the comparison, 49 - on the output 10 pulse shaper sync pulse width modulator. Moreover, the timing diagrams (figure 2) correspond to a multiphase pulse stabilizer, made of power converter cells; 38 - 43 (fig.Z) - from power converter cells; a 44 - 49 - out of 12 power converter cells. Multiphase switching regulator operates as follows. From the output of the generator, there are 5 clock pulses with a period of 0.01 T. K where T is the switching period of the power converter cells 2; K - required (in%) reproduction accuracy of the pulse duration of the output signal of the pulse-width modulator 11 at the input of the power converting cells 2, is fed to the input of the formers 6 and 7 clock pulses, Binary signals can be used as formers 6 and 7 clock pulses bit counters (for example, type K155IE5). At the same time, n is determined by the expression of the form xi 2, where rn is the number of power converter cells 2; M is the maximum possible number of power converting cells 2. The output voltages of the clock drivers 6 and 7, shown respectively on plots 2, 29 (FIG. 2), can generally have a phase shift. Their period TD T / m determines the required time offset between the electrical processes in the power converter cells 2. The output voltage of the clock generator 6 is used: to produce at the output of the driver 8 strobe pulses (plot 33, fig.-2) that coincide in time with a voltage front 1/0 (plot 22, FIG. 2) of the former 6; to synchronize the K-bit binary c counter 19; to synchronize the P / -r of the regular shift register 13. The number of bits of the binary counter 19 and the digital node 20 is determined by the maximum possible number of conversion phases 2 and is determined by the expression (M + l), (M + l), 2.3 Output signals at each of the K outputs The coding unit 21 can take two values: o low voltage level, high voltage level. Suppose that at the output of the first three low-order bits of the coding block 21, high levels of stresses are set, and from the fourth to K-th (with) - low levels. This means that at the output of the coding block 21 (respectively, at the output of the comparing node 20) the number 111 is set in the binary counting system corresponding to the number 7 in the decimal number system. At the same time, at the output of the digital node 20, a comparison of the turns of the signal (high voltage level) is only in the case when the output of all three lower-order bits of the K-bit counter 19 will simultaneously have high levels of voltages. This happens at time points toftA 2. / fcb (plots 39-42, fig.Z) at equal time intervals T - 7 Tz. In a counter 19 (Fig. 1) and at the output, the former 10 sawtooth voltage. This signal provides at the output of all K bits of the binary counter 19 of the occurrence of low voltage levels (plots 39-41., - FIG. 3) and at the output of the Forms of the body 10 of the saw-tooth voltage (plot 43, fig. 3). Fig. 3 (plots 44-49) shows the case when, at the output of the coding block, the number in the binary number system is 1100, corresponding to the number in the decimal number system. Thereafter, a reset of the K-bit counter 19 (plot 28-32, FIG. 2) and synchronization of the saw-tooth voltage generator 10 is performed at instants ti, i,, i (plot 48 and 49, FIG. 3) at equal intervals time T 12 - T. Thus, the installation. at the output of the coding block of the digit allows to form the period of the sawtooth voltage T in r times the period of the following T „clock pulses. As will be shown below, this allows the formation of uniformly shifted identical signals to control the mth number of power conversion phases. Obviously, the number of phases M is bounded above by the maximum possible number M, determined by the number of bits of registers 12 and 13 and, accordingly, by the number of control flip-flops 17, which in turn are selected from the condition of ensuring the functioning of the maximum possible number of meters of power converting cells 2 operating on the total load. Next, we consider the operation of a multiphase stabilizer at m N. A sawtooth voltage Un (t) with a period of following T (plot 23, Fig. 2) at the output of the former 10 and a constant voltage U (.. t (t) Ha output One of the comparison circuits 15 is used to form a pulse-width modulated signal with a pulse duration tu and a period T (plot 24, Fig. 2) at the output of the modulator 11. The indicated signal arrives at the information input of the shift register 13. The information is written by the shift register 13 1/0 clock pulses (plot 22, fig. 2), coming from the output of shaper 6 to the synchronization input of register 13. This ensures that the high voltage level of register 13 is at the output of the first discharge in time (plot 25, fig. 2) at the output of the second time p yes at the moment (plot 26, Lig.2), at the output of the Mth bit at the moment ± (n-1) T. In the general case, the duration of the pulses at the output of the register 13 (plots 25-27, Fig.2) differs from the duration of the pulses at the output of the pulse-width modulator 11 (plot 24, Fig. 2) by the value of O AttlVi. This error is in the prototype. The simultaneous presence of high levels at the inputs of the AND-16 logic elements ensures that the control level of the control trigger 17 is low and their installation in O. According to the time diagrams of the voltages at the input of the logic elements (plots 25-27, 30, 33, FIG. 2), at the output a of the first trigger. 17 is high at the moment at the moment, at the output of the second trigger 17 - at the moment, ..., at the output of the n-th trigger 17 - at the moment t- (M-l) T. Until the moment. universal M-bit register 12 is in the sequential receive mode with a right shift, since the low level is present at the information mode selection input

(plot 28, figure 2). Clock pulses from the output of the Lormirovator 7 (plot 29, figure 2) are fed to the synchronization input of the register 12 and provide at the time of the front 1/0 a record arriving at the low level information input. At the point in time (plot 24, Fig. 2) a low voltage level is generated at the output of the pulse-width modulator 11. According to the front of 1/0 of this signal, the driver 9 provides a short strobe pulse (plot 28, figure 2), which sets the driver (counter) 7 at the input R. into the high level and the register 12 at the input to the parallel reception mode. Since the input of the first bit is connected to the positive bus of the power supply source 18, and the inputs from the second to M bits are connected to the negative bus of the power supply source 18, at the time of the 1/0 strobe pulse, the output level is recorded for the first time the register bit 12 and low level in bits from the second to / K1-th. After the strobe-pulse expires, the shaper (counter 7) provides pulses with a period of Tt (starting from) at the synchronization output of the register 12, which has switched to the sequential receiving mode (at the information input). Recorded at the moment of time is the high level of preservation at the output of the first bit of register 12 in the time interval -tu: t4tu + Tn (plot 30, fig. 2). At the moment of time -t-tu + Tn, coinciding with the front 1/0 coming from the output of the imaging unit 7 to the clock synchronization input) and 12 clock pulses (plot 29, figure 2), a low level will be recorded for the first time (plot 30 2) of register 12, since a low level is present at the input (plot 28, figure 2), and a high level record in the second bit (plot 31, figure 2).

Thus, the register 12 has a high voltage level in Vits (with a duration equal to T,) r1a output of the first discharge at time instant -t tu, output of the second discharge at time instant + T, output of the Mth discharge at time time -fc-tu + (1Ч-1). Т (v. Since the input circuits of the register 12 are connected to the synchronization input C of the control flip-flops 17, then

The indicated times by the front 0/1 switch the control flip-flops 17 (at the input D there is a high level). Shapers, (counters) 6 and 7 have the same bit width. This ensures the formation of clock pulses with an equal period T ,, but with a phase shift, since the initial state of the driver (counter) 7

synchronized at time t-tu. As a result, at the output of the control trigger 17, we obtain pulse-modulated pulses (plots 34, 35, 37 of FIG. 2) equal to

according to the duration of the signal at the output of the pulse-width modulator 11. Their time shift by the value of TC provides a time shift of the electrical processes in the power converter cells 2. In

The following time periods of the processes are repeated as described above.

The present invention, in comparison with the basic prototype object, allows reducing the time and material costs of designing sources, increasing the unification of the entire device by unifying

as power converter cells, and the control unit.

These advantages are achieved due to the ability to control various amounts of power.

conversion cells (from 2 to M) change only the output signal of the coding block.

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Claims (1)

MULTI-PHASE. PULSE CTA / BILIZAT.OR voltage comprising a power circuit configured in the form of parallel I ^th power converter cells, each of which is connected to the input and output terminals and a control unit consisting of a generator sinhroim-. pulses, a pulse shaper / synchronization of a pulse-width modulator, an M-bit shift register, a universal shift register, m control triggers, NAND gates, two clock shapers, two strobe shapers, a voltage reference, an analog comparison unit, moreover, the analog comparison unit, one of the inputs is connected to a reference voltage source, the other to output terminals, and the output to one of the inputs of a pulse-width modulator, the other input of which is connected It is connected to the output of the pulse-width modulator of the pulse-width modulator, the output of the pulse-width modulator is connected to the information input of the M-bit shift register and through the second generator of strobe pulses to the inputs of the universal M-bit register and to the input of the setting to `` 0 '' of the second a pulse shaper whose output is connected to the synchronization input of the sequential reception mode of information of the universal M-bit register, and the input to the output of the clock generator and to the input of the first of the pulse shaper, the input of the pulse-width modulator of the pulse-width modulator is connected to the synchronization input of the M-bit shift register and <§ through the first shaper of the pulse pulses is connected to the inputs M of the logical elements AND-NOT, each output of the universal M-bit register is connected to the synchronization input of the corresponding control triggers, the outputs of which are connected to the control inputs of the power converter cells, characterized in that, in order to increase the functionality, introduced A K-bit binary counter, a k-bit digital comparison node and a modulating block, the input of the K-bit counter connected to the output of the first clock generator, and each of the outputs to the corresponding information inputs of the digital comparison node, the coding inputs of which are connected to the corresponding outputs of the coding unit, and the output is to the input of the installation in the `` 0 '' k-bit binary counter and to the input of the pulse generator of the pulse-width modulator. SU., .. 1070528