SU1226322A1 - Digital meter of alternating voltage level - Google Patents

Abstract

The invention relates to measurement in communication technology. The purpose of the invention is to improve the measurement accuracy. The device contains a comparator 1, a driver 2, a logic unit 3, a counter 4, a reversible counter 5, digital-to-analog converters DAL 6 and 8 and a source 7 of constant voltage. Introduction to the device of the D / A meter 8, the logic block and the formation of new connections between the elements of the device allows two sub-cycles of measurement (coarse and precise) transformation. Moreover, the D / A converter 6, producing a coarse conversion sub-cycle, makes it possible for the D / A converter 8 to produce a precise conversion sub-cycle at which the amplitude of the input variable signal is close to the voltage at the analog input of the DAL 8. The description of the circuit diagram of the logic unit is given. 2 Il. L 3Bf1 C (O (L

Description

The invention relates to measurements in a communication technique and can be used to measure the level of alternating voltage.

The aim of the invention is to increase the measurement accuracy by introducing two measurement sub-cycles — coarse and accurate conversion, and the effect of increasing the accuracy in the predictable meter is that the digital-to-analogue conversion stage, producing a coarse-conversion subcycle, enables the digital-to-analogue conversion (DAC) to perform an exact step. A sub-conversion of exact conversion, in which the amplitude of the input variable signal is close to the voltage at the analog input of the D / A converter.

Figure 1 shows the block diagram of the device; FIG. 2 is a conventional logic block diagram. The digital AC voltage level meter (FIG. 1) contains a comparator 1, the first input of which is connected to the input of the imaging unit 2 and is the device input, the output of the comparator I is connected to the first input of the logic unit 3, to the second input of which the output of the imaging device 2 is connected , a launch button output is connected to the third input. The first and second outputs of logic unit 3 are connected to the inputs of counter 4, the second and third outputs of logic unit 3 are connected to the inputs of: reversing counter 5. The outputs of counter 4 are connected to the digital inputs of digital-to-analog converter 6 and parallel to the digital computing unit. The analog input digital-to-analog converter 6 is connected to the output of a constant-voltage source 7.

The output of the digital-to-analog converter 6 is connected to the analog / input of the digital-to-analog converter 8. The digital inputs of the digital-to-analog converter 8 are connected to the outputs of the reversing counter 5 and in parallel with the computing unit. The output of the digital-to-analog converter 8 is connected to the second input of the comparator 1.

The device works as follows.

The measurement cycle starts by applying to the input. The start of logic block 3

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thirty

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of a short impulse of a positive pnness. After that, the outputs of the reversible counter 5 and the counter 4 are set to single and zero states, respectively, by applying to their installation inputs a pulse from the second output of the logic unit 3.

As a result, the output 6 will establish a voltage equal to zero, and the digital laboratory 8 will operate in the mode of voltage translation from the analog input to the output. In this way, the initial compensation voltage at the second input of comparator 1 will be zero.

The measurement cycle consists of two subcycles: coarse and precise measurement. In the first coarse sub-cycle, logical block 3 transmits pulses from input b to its first input J. Then, these pulses go to the counting input of counter 4. With each period of the input variable signal, the binary combination at the outputs of counter 4 increases by one and the voltage at the output of the DAC 6 increases by U2 This voltage is fed through the DAC 8 to the second input of the comparator 1, causes a narrowing of the pulses at the output of the latter with each period. When the value of the compensating voltage amplitude of the input signal is exceeded, the pulses at the output of comparator 1 disappear. This fact is registered by the logic unit 3, and it switches the translation of the pulse of the shaper 2 from the first output to the third i. From this moment begins the second - accurate measurement sub-cycle, during which the pulse from the output of the imaging unit 2 through the logic unit 3 is postulated to the subtractive input of the first reversible counter 5, which in each subsequent period reduces the binary -e combination at its outputs by one, all : 1 the consequence is that the compensating voltage at the output of the D / A converter 8 is reduced by A ,. At the moment of time, when the compensating voltage becomes greater than the amplitude of the input signal, the output of the comparator

1p is a pulse, which is registered by block 3. By this fact, logic block 3 stops broadcasting t: tMnynbcoB from the output of the driver

2 on its outputs and the measurement cycle ends. Binary combinations

 from the outputs of the reversible counter 5

and the counter 4 is fed to a digital computing unit, which performs the operation of dividing the readings of the reversible counter 5 by the readings of the counter 4 and provides a digital result of the amplitude of the input alternating voltage,

From the above description of the operation of a digital ac voltage level meter, it can be seen that the first coarse measurement subcycle ensures that the conditions are fulfilled when. source voltage 7 and divided

The DAC 6 is close to the amplitude of the input signal, and is fed to the analog input of the DSC 8, which participates in the second accurate measurement sub-loop. The logic block (figure 2), in which the Start input is connected to the clock input C of the D-flip-flop 9, information input D of which is connected to the bus of the logical unit, and the output is connected to the information input D of the second p-flip-flop 10, the output of which is connected to the first input of the first element 11, the output of which is connected to the output C of block 3 and the installation input R in trigger 9, and to the clock input C of the third D-trigger 12, information input D of which is connected to the bus of the logical unit, and the installation input R - to the setup input S of the RS flip-flop 13 and to the output in the second element And 14, the first input of which is connected to the output of the inverter 15 and to the clock input C of the fourth D-TRIGGER 16, and the second input to the inverse output of the same trigger 16, information input D, which is connected to the logical zero bus, and the installation input S - to the input e of the block 3 and to the installation input R of the RS flip-flop 13, the output of which is connected to the second input

 set to zeros and the fourth

D-flip-flop 16 to one. The pulses coming from the input b are inverted by the inverter 15. On the back edges of the received pulses, the fourth D-Trigger 16 enters a logical zero. But, however, pulses from the input of the fourth D TpHrrep 16 are set to the state of a logical unit, when the meter is in non-working and operating modes (respectively, the pulses at the comparator output have a duty cycle of 2 or are narrowed) at the inverse output of the fourth D-trigger 16, or 15 is supported a state of logical zero, or pulses appearing that fall within the intervals between the pulses at the output of the inverter 15. Thus, the coincidence at the inputs

20 of the second element AND 14 does not occur and at its output a constant of logic level zero is maintained.

And on the falling edge of the pulse fed to the Start input, the first

25 D-flip-flop 9 enters the logical unit, which is transferred to the second D-flip-flop 10 by the next falling edge of the pulses fed to input b, and as a result begins 30 with the translation of pulses from input b to output C through the first element II. The first impulse that passed to its output will set the first D-flip-flop 9 to the zero state, which is written,. It is also observed in the second D-thrnger 10 by the falling edge of the same pulse. As a result, a single impulse will pass to exit C, which will set the counters to the required states and

4Q, with its falling edge, will write down the logical unit to the third D-flip-flop 12, after which the transmission of pulses will start from the input L to the output d through the fourth element I 18. You will begin

the third element And 17, the output of which is 45 the completion of a rough measurement subcycle, is connected to the output i of block 3, and the first input to the input b to which the input of the inverter 15 is also connected, the clock input from the second D-flip-flop 10, the second inputs of the first 11, the third 1 7 and the fourth 18 elements And, the output of the latter is connected to the output J (counting input of the counter), and the first input to the output of the third D-flip-flop 12, functions as follows And 14, a logical unit will arrive. As a result, the weekend is

Before starting work, the B-triggers from the pulses of the inverter 15 will be received first through the third and the RS-trigger 13 to the output of the second element I 14. Tre

during which the input pulses .e narrow and disappear. At the first disappearance of the pulse at the input, the unit state of the fourth D-flip-flop 16 for the interval between two pulses at the output of the I5 inverter will not be restored, and from the inverse output of the fourth D-flip-flop 16 to the second input of the second elec 226322

set to zeros and the fourth

D-flip-flop 16 to one. The pulses coming from the input b are inverted by the inverter 15. On the back edges of the received pulses, a fourth zero is entered into the fourth D-flip-flop 16. But, however, pulses from the input of the fourth D TpHrrep 16 are set to the state of a logical unit, when the meter is in non-working and operating modes (respectively, the pulses at the comparator output have a duty cycle of 2 or are narrowed) at the inverse output of the fourth D-trigger 16, or 15 is supported a state of logical zero, or pulses appearing that fall within the intervals between the pulses at the output of the inverter 15. Thus, the coincidence at the inputs

20 of the second element AND 14 does not occur, and a logic zero level is constantly maintained at its output.

And on the falling edge of the pulse fed to the Start input, the first

25 D-flip-flop 9 enters the logical unit, which is transferred to the second D-flip-flop 10 by the next falling edge of the pulses fed to input b, and as a result begins 30 with the translation of pulses from input b to output C through the first element II. The first impulse that passed to its output will set the first D-flip-flop 9 to the zero state, which is written,. It is also observed in the second D-thrnger 10 by the falling edge of the same pulse. As a result, a single impulse will pass to exit C, which will set the counters to the required states and

4Q, with its falling edge, writes a logical unit to the third D-flip-flop 12, after which the translation of pulses from input L to output d through the fourth element I 18 begins. You will begin

the completion of a coarse subcycle of measurements, ment And 14, will be a logical unit. As a result, the weekend im-

during which the input pulses .e narrow and disappear. At the first disappearance of the pulse at the input, the unit state of the fourth D-flip-flop 16 for the interval between two pulses at the output of the I5 inverter will not be restored, and from the inverse output of the fourth D-flip-flop 16 to the second input of the second elet. tion, and the RS-trigger 13 in the unit, i.e. the pulses will be switched from input b to output i through the third element I 17. An exact measurement sub-cycle will begin, the completion of which will be the appearance of a pulse at the input b. According to it, RS-trigger 13 will be set to the zero state and the pulse transmission will stop.

Claims (1)

Invention Formula A digital voltage level meter containing a constant voltage source, a comparator, the first input of which is connected to the driver input and is the device input, the second comparator input / connected to the code of the digital-analog converter, the digital inputs of which are connected to the outputs of the reversible counter , characterized in that, in order to improve measurement accuracy, a counter, a second digital-to-analog converter, a logic unit, are entered into it, the first input of which is connected to the output of KOjvfflapaTOpa, second The second input is connected to the output of the imager, and the third input is connected to the start button, the second and third outputs of the logic unit are connected to the inputs of the reversible counter, and the first and second outputs of the logic unit are connected to the inputs of the inputted counter, the outputs of which are connected to the information inputs of the second digital-analogue converter, the analog input of which is connected to the output of a constant voltage source, and the output is connected to the analog input of the first digital-to-analog converter, in addition, the information inputs of the digital a-analog converters are also connected to computing Jtycn fgg.g Editor R. Tsitsika Compiled by V.Shubin Tehred L.Oleinik Order 2125/42 Circulation 728 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 .-Production and printing company, Uzhgorod, Projecto st., 4 Proofreader L. Patay