SU1297003A1 - Device for determining time position of absolute maximum in signal implementation - Google Patents

Abstract

The invention relates to a measurement technique and can be used to measure the flow rate of liquids and gases, in statistical radio engineering when determining the temporal position of pulses, etc. The purpose of the invention is to improve the accuracy of determining the temporal position of the absolute maximum in the realization of a signal. The goal is achieved by eliminating influence of the non-identity of the reference and signal channels, the amplitude of the signal, the mixing of zero and the unequal magnitude of the gain of the comparator and a more accurate fixation magsi- absolute position of the minimum of the signal. The greatest gains are achieved with slowly varying signals. The device contains trigger 1, element 2, counters 3 and 19, 4 clock pulse generator, comparator 5, code reading unit 20, register 21, decoder 22, indicator 23. Digital to analogue converter 8, reversible counter 7, block 10 comparison of codes, register 9 triggers 6 and 15, elements 11, 12, 16, 17, 18, counters 13, 14, 24, new functional connections were formed. 2 Il. I (L

Description

The invention relates to a measuring technique and can be used to measure the velocity of a stream of liquid and gases, in statistical radio engineering when determining the time position of pulses, etc.

The purpose of the invention is to improve the accuracy of determining the temporal position of the absolute maximum in the implementation of a signal by eliminating the influence of the nonidentity of the reference and signal channels, the amplitude of the signal, the offset and the final magnitude of the comparator gain and more accurate

fixing the time position of the element by the stroke of the element I 2, and the S input from the maximum signal maximum. At the most elemental rate of AND 18 and the input, the synchronized gain is achieved with slowly varying signals.

Figure 1 shows the block diagram of the device; Fig. 2 shows the diagrams depicting his work.

The device contains a trigger 1, the element And 2 and the counter 3, the reset input of which is connected to the S-input of the trigger 1 and the Start bus, and the output - with time.

The R-input of the trigger 1, the generator 4 as well. On the Start signal, the output pulses are produced, the direct output of which is the reset of the counter 3 and the registers 9 and the trigger 1 is turned on. The counting pulses (fig 2g) from the direct output of the generator 30 4 clock pulses through element And 2 is fed to the counting input of the counter 3, which, after overflow, generates a Stop signal. Resetting the register 9, the synchronization input of the register 21 is connected to the output of counter 3, the counter 24, the counting input of which is connected to the output of the element 16, the reset input to the output of the element 17, and the output to the second input of the code reading unit 20.

The device operates as follows: it is connected to the second input of the I 2 element, comparator 5, the signal input of which is connected to the bus. Input, trigger 6) whose D input is connected to the output of comparator 5, and the C input to the inverse generator output of 4 clock pulses, reversing counter 7, the counting input of which is connected to the direct output of the 4-clock pulse generator, the input of the reverse control to the inverse output of the trigger 6, and the output through the digital-to-analogue trigger 1, as a result of which 35 the measuring interval (fig.2a) of time T t is formed -t. The comparator 5, the trigger 6, the reversing one, the counter 7 and the DAC 8 form an analog-to-digital converter (A / D converter) and a tracking converter (D / A converter) 8 - with a support type.

the input of the comparator 5, and the reference input of the DAC 8 is connected to the reference voltage bus C, connected in series with the output of counter 7, register 9 and block 10 of code comparison, the second input of which is connected to the output of counter 7, and the reset input of register 9 with the start bus , elements 11 and 12, the first inputs of which are connected to the direct output of the generator 4 clock pulses, and the second - respectively to the direct and inverse outputs of the trigger 6, counters 13 and 14, the counting inputs of which are connected respectively to the outputs of the elements 11 and 12 , and reset inputs -retarded with direct and inverse outputs of the flip-flop 6, the trigger 15, S and R-inputs of which are connected respectively with

five

970032

the outputs of the counters 13 and 14, the elements 16, 17 and 18 And, the second inputs of the elements And 17 and 18 and the third input of the element 16 is connected to the output of the block 10 comparison codes, the first inputs of the elements And 17 and 18, respectively, with the outputs of the counters 13 and 14, the first input element AND 16 - with the inverse output of the trigger 6, and the second input - with the output of the trigger 15, - serially connected counter 19, block 20 of the code subtraction, register 21, decoder 22 and indicator 23, and the counting input of counter 19 is connected to the upper

the element 2 and the S-input - with the output of the element 18 and the input

at once.

register 9, the synchronization input of register 21 is connected to the output of counter 3, counter 24, the counting input of which is connected to the output of element AND 16, the input input to the output of element And 17, and the output to the second input of block 20 of the code subtraction.

The device works as follows the trigger 1, as a result of which the measuring interval (fig. 2a) of time T t -t is formed. Comparator 5, trigger 6, reversible, counter 7 and DAC 8 form an analog-to-digital converter (ADC). Next, the magnitude of the reference voltage U of the DAC 8, the frequency f of the generator 4 and the number of binary bits of the reversible counter 7 and DAC 8 are selected from

and

X max

n Ig 2 K;

dU

dt

2L I t

Max

50

f - 2

where and

five

 - the greatest value

input signal, K - gain

comparator 5.

When the signal U arrives at the input of the following ADC, the output of the comparator 5 and the direct and inverse outputs of the trigger 6 form the corresponding 31

but sequences of impulses (figs, 2c, d, e). The pulse sequences (figd, e) from the direct and inverse outputs of the trigger 6 arrive at the inputs of the elements 11 and 12, respectively, to the other inputs of which pulses arrive (figure 22) from the direct output of the generator 4 clock pulses. At the outputs of the elements 11 and 12, respectively, a sequence of pulses are formed (FIG. 2g, h). Moreover, the appearance of pulses (FIG. 2g) corresponds to an increase in the stepped b-thorny signal (FIG. 2b) from the output of the CDL 8, ) - its decrease. Pulse sequences (2g, h) are delivered to the counting inputs, respectively, of counters 13 and 14, the reset inputs of which are received respectively by a sequence of pulses (Fig. 2e) Counters 13 and 14 are modulo meters 3, the outputs of which after resetting a pulse appears after the second and every (m -1) subsequent (until reset) counting pulses. Figure 2 shows the operation of the device using counters 13 and 14 modulo.

At the output of counter 13, a pulse sequence (fig.2i) corresponds to the rise of the input signal and JJ is formed as a result of counting, and at the output of counter 14 - a pulse sequence (fig.2k) corresponding to a decrease in the level of the input signal U. Trigger 15 forms intervals time (fig.2l) from the beginning of the rise of the input signal U to the beginning of the decay U, i.e. according to the sequence (ig ig.2i) from the counter 13, the trigger 15 is energized, and reset by the sequence (fig 2k) from the counter 14. Since at the initial time moment t the register 9 is reset to the zero state, then at the output of the block A code comparison 10 sets a signal (Fig. 2m), indicating that counter code 7, proportional to the current value of the reference signal level (Fig. 26), is larger than register code 9, and allowing signals to pass through AND elements 16-18.

The signals (Figs. 2 and 1, k) from counters 13 and 14, the passage through And 17 and 18 elements set the counters 24 and 19 to their initial state. Moreover, the counter 24 is reset to the zero state.

034

and the subtracting counter 19 is set to the state corresponding to the volume of the counter 3,

The counter 24 starts counting after each pulse in the sequence (Fig. 2i) that passed through the element And 17. Starting from the time t, the input signal and changes within one step of the output voltage of the CLP 8. This results in a counter 24 during the interval time from t to t the code is written, the numerical value of which is equal to the integer part () fp / 2, since from the inverse

trigger output 6 through the element And 16 to the counting input of the counter 24 comes at this time a sequence of pulses with a frequency fg / 2.

Account lasts until time

t, when after the first two drops of the next step signal (Fig. 2b), the trigger 15 is reset and the counting pulses through the AND 16 element are prohibited.

At the same time, the counter 19 is reset to the initial state and the counting of pulses begins at a frequency f from the forward generator output of 4 clock pulses that have passed

through the element and 2.

Simultaneously with the installation of the counter 19 pulses (fig.2n) from the output of the element 18, the write to the register 9 of the code K1 from the output of the counter is made

7, corresponding to the level of the reference signal (FIG. 26) at time t. At the output of the code comparison unit 10, the enabling signal disappears (Fig. 2m) and the elements AND 16-18 are locked. The permissive signal (Fig. 2m) appears only after the reference signal (Fig. 26) exceeds the level corresponding to the K1 code, after which the operation of the device is similar to that in

inte; 9c - time () ..

At time t, an impulse appears once again at the output of element And 18. Counter 19 is reset and starts counting down. In register 9, K2 code is recorded (Fig. 2). In counter 24, part of the number (t,) is intact.

If before the end of time T the signal level (Fig. 26) does not exceed

the level corresponding to the K2 code of register 9, then all subsequent pulses after time t do not pass through elements 16-18. After the time T has expired, the return count of the second counter 19 stops (trigger 1 and closes element 2), from which the code arrives at the summing input of C5 block 20 from reading codes, the code from the output of counter 24 enters the input expensive, the code difference from the output The code reading unit 20 at the moment of time t with the pulse of the overflow of the counter JO of the chip 3 is rewritten into the register 21, from which through the decoder 22 it goes to the indicator 23 where the information is displayed. At time tj, the number N is recorded in the counter 24, and at time t (the end of the measurement time), the number N 2 (T – T) fg.Ha is written in the counter 19 and the output of the code reading unit 20 is set to 20 code NH - N , (, / 2) „T f. This code value is proportional to the time T, equal to

L

time from the beginning of the measurement t to the moment t of the passage of the absolute maximum signal peak 25,

Obviously, the measurement error is almost independent of the zero offset of comparator 5, since the extremes of the input signal and the output-30 (approximating) signal of the DAC 8 coincide in time with the approximation error yes 1 / fo, where. f о - frequency of the generator 4 clock pulses .35

Claims (1)

Invention Formula A device for determining the temporal position of the absolute maximum in the signal realization, containing the first trigger, the direct output of which is connected to the first input of the first element And whose output is connected to the counting inputs of the first and second counters, the output of the first counter 45 is connected to the synchronous input of the first register and the R input of the first trigger, and the reset input of the first counter connected to the S input of the first trigger and to the Start bus, a generator of clock pulses 50 pulses, the direct output of which is connected to the second input of the first element comparator, a signal input coupled to the bus entrance, the second counter outputs 55 are connected to a summing input of subtractor block codes, you} soda connected in series through which the first register and a decoder is connected to the indicator inputs, characterized in that, in order to improve accuracy, a digital-to-analog converter, a reversible counter, a code comparison unit, a second register, the second and third triggers, the second, third, fourth, fifth and sixth elements, and the third are entered into it. , the fourth and fifth counters, with the direct output of the clock generator connected to the first inputs of the second and third elements NfeHTOB I and to the counting input of the reversible counter, the input controlling the reverse of which is connected to the inverse output of the second three a second second input element And the third input of the third counter and the first input of the fourth element And, the second input of which is connected to the direct output of the third trigger, the S input of which is connected to the output of the third counter and the first input of the fifth element And R input The third trigger is connected to the output of the fourth counter and the first input of the sixth element I, the output of which is connected to the S input of the second counter and the synchronous input of the second register, the reset input of which is connected to the Start bus, and the outputs to the first inputs of the code comparison block, the second inputs of which are connected to the outputs of the reversible counter, information inputs of the second register and information inputs of the digital-analog converter, the signal input of which is connected to the reference voltage bus, and the output - to the reference input of the comparator, the output of which is connected to the D input of the second trigger, C input which is connected to the inverse output of the clock pulse generator, and the direct output to the second input of the second element AND and the reset input of the fourth counter D} whose counting input is connected to the output of the third ele And the counting input of the third counter is connected to the output of the second element And, the output of the code comparison unit is connected to the second inputs of the fifth and sixth elements And to the third input of the fourth element And, the output of which is connected to the counting input of the fifth counter, the reset input of which connected to the output of the first element I, and the outputs to the subtractive input of the code reading unit. 6 i d e Well 3 and k l Not and PPPPPPPP P PPP-1PPP P PPPP P PPPP 1 PPPP P PPPP P PSPPPPPP PPPPPG fliiniimniminniiii n on pop puppy and fan flnnnn n n nnnniinnii n n posposum JULfliBLnnii 1 I i i i one I i i eleven Jl 1-1PPP P PPPP P PPP P PSPGPPP PPPPPPG -t t f t -t t -t -t pop puppy and fan n pposymmJULfliBLnnii  i one i i eleven Editor I. Casarda Compiled by L..Pletneva Tehred A. Kravchuk Proofreader, Cherni 778/50 Circulation 371 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FIG. 2