SU1259470A1 - Digital generator of linear-frequency-modulated signals - Google Patents

Abstract

The invention relates to radio engineering and provides an extension of the operating frequency range. The control code generator (CCF) 3 sets the parameter codes of the generated linear frequency modulated signals (LCM). A clock generator 2, together with a FUC 3 and a controlled frequency divider 1, determines the desired slope of change of the frequency of the PMS. The FCS 3, together with the coincidence unit 5 and the counter 4, determine the values of the initial and final frequency of the formed LPMC. The code from the counter 4 enters the phase storage 6, the control frequency divider 1 determines the time interval during which the output counter does not change, and therefore the frequency of the generated signal does not change, the output 2n the higher bits of the phase accumulator 6, the code of the current phase of the corresponding frequency is fed to the corresponding address inputs of the memory unit (KB) 7, and from the outputs (N-1) of the higher bits - to the address inputs of the KB 8. The BR 7 is programmed to the main one, and the WH 8 - on the correction function of the initial function tion Sin H The values of the output code of the correction function are determined by the signals received on the corresponding address inputs of the KB B with N younger bits of the phase accumulator 6. The Coarse Sine Codes and the codes of the Correction Function reach the exact value of the sine to the Sumat 9. Sin (h) through the DAC 10 and the low-pass filter 11 is output. 1 il. I (L with SP 4

Description

The invention relates to radio engineering and can be used to form pine-frequency-modulated (chirp) signals in various short-wave communication systems, seismology, radar.

The purpose of the invention is to expand the working frequency range.

The layout of the proposed digital chirp signal generator is presented on the chipset.

The digital chirp signal shaper contains a controlled frequency divider 1, a generator of 2 clock pulses, a driver of control codes 3, a counter 4, a coincidence unit 5, a phase storage 6, a first memory block 7, a second memory block 8, an adder 9, a digital-analog tax converter (DAC) 10, low pass filter 1t (LPF).

The digital shaper of chirp signals works as follows.

The shaper 3 control codes sets the codes of the parameters of these chirp lines generated: the initial frequency code (К), the final frequency code (К |) and the code of the time interval of a constant value of the phase increment of the given frequency (Cd). A clock generator 2, together with a driver 3 and a controlled frequency divider 1, determines the required slope for changing the frequency of the chirp signal. The imaging unit 3, together with the coincidence unit 5 and the counter 4, determines the values of the initial and final frequency of the chirp signal generated. Phase storage 6 is a multi-bit accumulating adder.

The synthesis of the chirp signal is produced by changing at certain points in time the decoded frequency with a given step. In the initial state, in the controlled divider 1, the frequency is written down the code (Cd), which determines the time interval of the formation of one frequency

T

im t

- to

m.

where is t. - the period of the following clock pulses of the generator 2.

Counter 4 contains the code (K,) of the initial frequency of the signal being formed. On one of the inputs of block 5 of the match receives the code of the final frequency

(K) generated signal. Specified values of K, K, and K codes The 3 control codes of the generated chirp signal, which may consist, for example, of three multi-digit code switches, come from the driver of the 3 control codes. The output multi-digit code from the output of the counter 4 is fed to the second information input of the coincidence unit 5 and to the input of the phase storage 6.

The pulses from the generator 2 clocks of pulses are fed to the control inputs of the controlled frequency divider 1, the coincidence unit 5 and the recording input of the phase accumulator 6. In the phase accumulator 6 with the arrival of each clock pulse, the input code of the specified frequency coming from counter 4, with the currently existing output code. This operation is nothing but a change in the phase of the generated signal by an amount determined by the output code of counter 4, whose code at the initial moment-time is equal to the input code of the initial frequency (Cc) coming from the code of the driver 4.

The control divider 1 frequency transmits to its output only those input pulses whose numbers are multiples of the recorded code (Kj.)

arriving from one of the outputs of the imaging unit 3, and determines the time interval, and the flow of which the output code of the counter 4 does not change, and therefore, the frequency of the generated signal does not change. Each output impulse from the controlled divider 1 frequency is fed to the counting one. the input of counter 4, changing its output code by one, which corresponds to a change in the frequency of the output signal by an amount that is determined by the frequency of the generator 2 clock pulses and the size of the phase drive b

50

uF F.

TG

where n is the size of phase storage 6;

-frequency of following pulses;

- step of changing the frequency of the output signal.

3

The slope of the change in the output chirp signal is also determined and determined by the frequency of the generator 2 and the code K

Upon reaching the output code of the counter 4, the final frequency code (K), block 5, which is a multientry element, and passes the first pulse from the generator output 2 clock pulses to the control input of counter 4, sets the output frequency code at its output, returning the whole system is in its original state.

From the higher-order bits of the phase accumulator 6N, the current phase of the corresponding frequency goes to the N address inputs of the first storage unit 7. The code from the outputs (N-1) of the higher bits of the phase accumulator 6 is fed to the (N-1) higher address inputs of the second storage unit 8, respectively.

The first storage unit 7 is programmed to the main SinCH j), and the second storage unit 8 to the corrective fp (+ JaW) representation function of the original sine function SinCtf), where SinCM) is the value of the function on the Lth subband at the i-th argument point ( phases); i () is the value of the function of the t-th subrange at the point (i + j) of the argument.

Both Sin (4j) and EE-MF + Odc functions are specified in the form of tables programmed in memory blocks 7 and 8.

One of the tables sets the values of Sin (4, -) in some tchkakh () with a certain interval, the other of the table - the exact values of f. (if; +344) for each of these intervals, and the entire interval for changing the ti-bit of the bottom argument (phase) includes 2 nodal points, from which 2 subbands are calculated.

The value of the initial sinusoidal function Sin (v) in sub-band C at the point (4j JAtp) is defined as the sum of the values of the sinusoidal function Sin () at the nodal point (H () and the value of the correction function (4 ,. tJAVf) at the point (.f ) corresponding to the current phase.

Only one correction function is used for each subband. To determine the value of the sine function between nodes 259470-4

 By the dots, it is necessary that the correction function is determined at the points of the argument.

Then the total amount of blocks 7 and 5–8 of storage for storing the values of the sinusoidal function at the nodal points of the SinC) and the correction functions f (P. Ju4) is determined by

2 -h

sin

  7 t / id - n

t

ts

20

five

where -2 is the number of block cells

the memories in which the sine values of g are stored are at nodal points; 2 - the number of cells in which the values of one correction function are stored; 2 - the number of corrective functions in the entire interval of change of the argument (phase);

S is the number of used output high-order bits of the phase accumulator. The values of the output code of the correction function are determined by the signals 0 received by 1M11 to the N lower addresses of the inputs of the second storage unit 8 from the corresponding N outputs of the lower bits of the phase accumulator 6. The output codes of the coarse sine value 5 and the codes of the values of the correction function to the exact value the sine is received respectively from the outputs of the first and second blocks 7 and 8 of memorization to the inputs of cy # faTopa 9. 0 As a result of summing up the codes of the main and the correction function, the code of the sinusoidal function is obtained at the output of the adder 9 Sin (M) SinXM-j) + ((h -ju4), from 5 koto- cerned to DAC 10 is formed corresponding to the analog voltage values of the sinusoid.

The low-pass filter 11 generates a harmonic 0 sinusoidal signal from the step voltage signal.

Claims (1)

Invention Formula A digital shaper of linearly-5 frequency-modulated signals containing a shaper of control codes, the output of which initial frequency code is connected to information the input of the counter, the phase naKonvtrenb, whose recording input is connected to the output of the clock generator, the information inputs to the discharge outputs of the counter, and the outputs of the 2N most significant bits to the corresponding address inputs of the first storage unit, and the series-connected adder, digital-analogue converter and lower filter frequency, while the first input of the adder is connected to the output of the first storage unit, characterized in that, in order to expand the working frequency range, a second storage unit is inserted into it, each One of the higher address inputs of which is connected to the corresponding one of the (N-1) outputs of the higher-order bits of the phase accumulator, and each of the best address inputs Editor L. Gratshsho Compiled by G. Zakharchenko Tehred A. Kravchuk. Proofreader L-Zimokosov Order 5138/57 Circulation 816. Subscription VNIIPI USSR State Committee for inventions and discoveries 11S035, Moscow, Zh-35, Raushsk nab. d. D / 5 Tronesvo-printing company, Uzhgorod, st. Project, 4 inputs - with the corresponding of the N outputs of the lower bits of the phase accumulator, the output - with the second input of the adder, the coincidence unit, the first and second information inputs of which are connected respectively with the output of the final frequency code of the control generator of control codes and the output of the counter, the control input - with the output of the clock pulse generator, and the output is connected to the counter recording input, as well as a controlled frequency divider, the signal input of which is connected to the output of the time interval code of a constant value of the phase increment of a given h Costs, control code generators, the control input is with the output of the clock generator, and the output is connected to the counting input of the counter.