SU1465956A1 - Shaper of signals of random shape - Google Patents

Abstract

The invention relates to a pulse technique and can be used in measuring devices. The purpose of the invention is to improve the accuracy of the formation of arbitrary waveforms by applying a variable quantization step over time. To achieve the goal, a shaper digital-to-analog converter 24, an operational amplifier 25, a clock generator 1 and a data bus 27 are included in the driver, and elements 2, 5, 17, 20, 21, 22, dividers 3, 9, 10 are entered. , triggers 4, 12, 15, elements OR 7, 8, 11, 13, 14, shift register 18, element NOT 19, adder 23. Each interval of the stepwise approximation of the generated signal is encoded by three code bits in register 18. One of These bits encode the quantization step in time, and the other two encode the magnitude and sign of the voltage increment interval. The information about the generated signal is recorded in the register 18 from the bus 27 by pulse on the bus 28 Record. Then information. sequentially out of register 18. Divisor 10 provides a shift of three bits in each home interval. Maximum duration A) with

Description

one

The invention relates to a pulsed technique and is intended for use with measuring devices.

The purpose of the invention is to increase the accuracy of the formation of arbitrary waveforms by applying a variable quantization step over time. .

Figure 1 shows a functional diagram of an arbitrary waveform generator; 2 is a timing diagram explaining its operation j in FIG. 3 is a graph of the generated signal.

A free-form signalformer shaper contains a clock generator 1, the first element AND 2, the first divider 3 frequencies, the first trigger 4, the second element AND 5, the bus 6 Set zero, the first element OR 7, the second element OR 8 "the second divider 9 frequencies, third frequency divider 10, third element OR 11, second trigger 12e fourth element OR 13, five elements OR 14, third trigger 15, bus 16 Start, third element 17, shift register 18, element 19, fourth element And 20, the five element And 21, the sixth element And 22, the adder 23, the digital-analog converter s 24, operatsion- ny amplifier 25, the output bus 26, bus 27 and data bus 28 Record.

The first input of the first element And 2 is connected to the output of the clock generator 1, the single output of the first trigger 4 is connected to the second input of the first element 2, the output of which is connected to the first input of the second element 5 and the first divider 3 of the frequency, the output of which is connected to the first input of the second element ШШ 8, the second input

0

five

0

five

0

go connected to the output of the second element And 5, the second input of which is connected to the output of the third trigger 15, the bus 6 is connected to the first input of the first element OR 7, the setup input of the shift register 18, the installation input of the adder 23, the output of the first element OR 7 is connected to the zero input the first trigger 4, the installation input of the first frequency divider 3, the installation input of the third frequency divider 10, the first input of the fourth element OR 13 and the first input of the fifth element OR 14, the output of which is connected to the zero input of the third trigger 15, the unit input of which is connected to the output of the fourth element AND 20, the bus 16 is connected to the single input of the first trigger 4, the installation input of the second frequency divider 9 and the first input of the third element OR 11, the second input of which is connected to the output of the third frequency divider 10, and the output - to the single input of the second trigger

12, the zero input of which is connected to the output of the fourth element OR

13, and the output - with the first inputs of the third 17, fourth 20, p that 21

and the sixth 22 elements And, the output of the second element OR 8 is connected to the input of the second frequency divider 9, the input of the third frequency divider 10, the second input of the fourth element OR 13 and the shift input of the register 18, the output of the second frequency divider 9 is connected to the second input of the first element OR 7 , the first output of register 18 is connected to the input of register 18, the data of which is bitwise connected to bus 27, bus 28 is connected to input of register 18, the second output of which is connected

with the second input of the third element And 17 and the input element NOT 19, the third. the output of the register 18 is connected to the second input of the fifth element I 21 and the fourth output to the second input of the sixth element And 22, the output of which is connected to the subtractive input of the adder 23, the summing input of which is connected to the output of the fifth element And 21, and the output to the input digital-to-analog converter 24, the output of which is connected to the input of the operational amplifier 25, the output of which is connected to the output bus 26, the output of the element HE 19 is connected to the second input of the fourth element And 20, the output of the third element And 17 is connected to the second input of the fifth element OR 14, the zero output of the first trigger 4 is connected to the third input of the fourth element OR 13.

The first frequency divider 3 has a division factor equal to n, where n is the register resolution 18,

The second divider 9 is the frequency of the coefficient (dividing agent, paBHbDi p, where n is the register size 18, the first account input and the second setting input, and is intended to fix the end of the formation of the signal immediately after one full cyclic shift of information in register 18.

The third frequency divider 10 has a division factor equal to three, and is intended to generate a polling signal for the second, third, and fourth outputs of register 18.

Register 18 has n data inputs for parallel writing a digital sequence of the generated signal code, a shift for receiving a signal when cyclically rewriting the contents of a shift register 18, a setup input for setting the initial zero state of all bits of a register 18, an input for cyclically rewriting the contents of a register 18, write entry to enable the recording of information in the register 18 with its data inputs, the first output for cyclic rewriting contained in the information register 18, the second output for reading info the higher n-th bit of register 18, the third output for reading information from the (n-1) -th digit of the register

14659564

18, a quarter B output for reading information from the (p-2) -th bit of the register 18. Register 18 is intended for parallel reception, sequential cyclic rewriting of the digital sequence of the code of the generated signal, as well as for its triad read. 10 Adder 23 may be executed in the form of a reversible counter.

The arbitrary waveform generator works as follows.

At time t (not shown), a single pulse is applied to the bus 6, which sets the register 18 to the zero state, the first trigger 4, the third frequency divider 10, the second trigger 12, the third

trigger 15, the first 3 frequency divider and adder 23.

five

At time t, bus 27 supplies the entire digital sequence of the generated signal code, which is written to register 18 when a single pulse arrives at the input of register 18 through bus 28. The sequence is divided into triads. The first bit of each triad contains information about the shift along the time axis (t), and the unit in this bit indicates a shift by one step, zero indicates that there is no shift and the content of the second and third bits of this triad is not the following , and to the current step, i.e. there is a shift by one step only on the level axis (V). The second and third bits of the triads contain information about the nature of the shift in V, namely: state 10 in these bits indicates a one-step increment in V relative to the previous step, 01 is a one-step decrease in V relative to the previous step and 00 - off-; - Because of the change in V relative to the previous step, state 11 is prohibited.

The arbitrary waveform former is ready to form a signal.

At time t3, a single pulse arrives on the bus 16 g, which sets the zero state to the second divider 9 frequencies and converts the first trigger 4 and the second trigger to the single state

five

0

12 (through the third element OR 1 TU, the voltage of the logical unit from the output of the second trigger 12 goes to the first inputs of the third 17, the fourth 20J of the first 21 and the sixth 22 of the elements AND, If the third output of the register 18 has a voltage A logical unit, then it goes through the fifth fifth element I 21 to the summing input of the adder J23 and is summed in it. If the fourth output of the register 18 contains the voltage of the logical unit, then it is through the sixth element And 122 enters the subtracted 5th input of summator 23 and is subtracted from its content The presence of a voltage of a logical unit at the third and fourth fifth inputs of the register 1.8 is simultaneously | impossible If at the second output of register 18 there is a direct, invertort zero by an element HE 19, goes through an open quarter element | and 20 to a single input of the third trigger jrepa 15 "converting it to a single | state. The voltage of the logical | unit from the output of the third trigger 15 goes to the second input of the second | element And 5, open it. If; on the second output of register 18, there is a load of logical unity, then the third trigger 15 does not change its state, as a result of which the second element And 5 remains closed.

For example, the logical unit from the unit output of the first trigger 4 enters the second input of the first element I 2, thereby allowing the passage of clock pulses from the output of the clock generator 1. The tact I1 pulses go to the count input of the first divider 3 frequencies and the first the input of the second element And 5, EC. PI at the second input of the second element And 5 there is a voltage of logical zero, that is, e. If the second output of register 18 contains the numerical value of a logical unit, then the second element I 5 does not pass clock pulses to its output. A pulse at the output of the first frequency divider 3 is formed when they calculate the clock pulses. This impulse, passed through the second element. OR 8, will go to the inputs of the second 9 and one third ° of its 10 frequency dividers, through even

the set element OR 13 will set the second trigger 12 to the zero state and will shift the contents of register 18 cyclically. This is repeated three times. After the third pulse arrives at the first counting input of the frequency divider 10, a single pulse is passed on its output, which through the third element OR 11 translates the second trigger 12 into a single state. The voltage of the logical unit from the output of the second trigger 12 is supplied to the first inputs of the third 17, fourth 20, 21, and sixth 22 elements I. The voltage of the logical unit from the third or fourth outputs of the register 18 goes to the summing or subtracting inputs of the adder 23, adding or subtracted from its contents, which in turn is fed to the input of a digital-to-analogue converter 24, which converts the contents of the adder 23 into a step-shaped voltage supplied to the input of the operational amplifier 25, which forms from The analog signal of allowance given to the output line 26. If the output of the second register 18 is present voltage logic-one, the work arbitrary waveform shaper further repeats the above-described algorithm. If the second output of register 18 contains the voltage of logical zero, it is inverted by the element NOT 19 and through the open fourth element AND 20 translates the third trigger 15 into a single state. The voltage of the logical unit from the output of the third trigger 15 is fed to the second input of the second element And 5, opening it. The clock pulses from the output of the first element AND 2, the passage through the second element AND 5, arrive at the output of the second element OR 8 and are fed to the inputs of the second 9 and third 10 frequency dividers. The first impulse translates the second trigger 12 to the zero state. The clock pulses from the output of the second element OR 8 shift the contents of register 18. When the contents of the register are shifted by three bits, the output of the third divider 10 frequency will have a pulse, which will translate the second trigger 12 into one state. The voltage of the logical unit at the output of the trigger 12 will open the third 17, the fourth 20, the fifth 21 and the sixth 22 elements I. The contents of the second and third bits of the register 18 will be summed up or subtracted in the adder 23, changing or leaving its contents unchanged.

If at the second output of register 18 there is a voltage of logical zero, then the operation of the driver proceeds according to the algorithm described above until it appears when polling the second voltage output of a logical one (scts.

The shaper will operate until a pulse frequency appears at the output of the second divider 9, which indicates that the generated signal is fully synthesized, i.e. the contents of register 18 have completed one rewrite cycle. This pulse through the first element OR 7 goes to the zero input of the first trigger 4, converting it to the zero state, and at its single output the voltage of the logical zero that goes to the second input of the first element I 2, thus prohibiting the passage of clock pulses on his way out. This completes the operation of the signal conditioner.

If it is necessary to form the next signal, a single impulse arrives at bus 16 and the driver will start working according to the algorithm described above.

Consider a specific example of the operation of the arbitrary waveform generator (figure 2).

At time t, (not shown), a single impulse is applied to the bus 6 which sets the blocks 18, 4, 10,12, 15, 3 and 23 to the zero state.

At time t (not shown), a 39-bit digital sequence of the generated signal code is supplied to the bus 27 in parallel form: 010 010 010 010 010 110 100 001 001 001 001 001 101. A single pulse is fed to the bus 28 and information is written to block 18 on triads:

010 is the first triad (recorded in the high order bits of register 18);

0

five

0

five

0

five

0

five

0

five

010 - the second triad; 010 is the third triad; 010 is the fourth triad 010 is the n triad; 110 - pole triad;

100- the seventh triad; 001 - the eighth triad; 001 is the virgin triad; 001 is the tenth triad;

001 - the eleventh triad; 001 - the twelve triad;

101- thirteen triad (recorded in the lower bits of register 18).

The arbitrary waveform former is ready to form a signal. At time tj (Fig. 26), the bus 16 receives a pulse, setting the frequency divider 9 to the zero state and triggering the trigger state 4 and the trigger 12 to the single state. At the output of the trigger 12, the voltage of the logical unit appears (FIG. 2g), which denotes the element AND 17, 20, 21, and 22. Since the first bit of the first triad contains a logical zero, the output of the element 20 appears to be a voltage of the logical unit (Fig.2i), which will translate into one state trigger 15 (figs). Since a logical unit is recorded in the second bit of the first triad, the output of the element 21 is Vits, the voltage of the logical unit (Fig. 2k), which goes to. the summing input of the adder 23. The contents of the adder 23 will go to the input of the digital-to-analog converter 24, the output of which will contain a signal proportional to the contents of the adder 23, i.e. unit, (Fig.2m).

The voltage of the logical unit from the output of the trigger 4 will allow the passage through the element AND 2 clock pulses from the clock generator 1. Since the voltage of the logical unit from the trigger 13 is present at the second input of the element AND 5, the output pulses of the element OR 8 will receive clock pulses (Fig 2d), the first clock pulse from the output of the element OR 8 will set the trigger 12 to the zero state and polling of the 39th, 38th and 37th bits of the register 18 stops (fig.2d, g, u, k). The same clock pulse shifts

the contents of register 18 by one bit, the second one TAKTOVLV pulse from the element OR 8 shifts the contents of register 18 by one bit, the third one by one bit. Now, the third high bits of register 18 contain the second tria of the digital sequence the code of the generated signal is 010. The same pulse passes to the output of the frequency divider 10 and transmits trigger 12 into a single state (Fig. 2e, g). The voltage of the logical unit from the output of the trigger 12 polls the high bits of register 18, Since the first discharge of the second triad contains a logical zero, the trigger. 15 maintains its state, the Single Impulse from the second bit of the cyan-1 is passed through. And 21 (fig. 2k) with the content of adder 23, which is converted by digital-analogue converter 24 (fig.2m). The above algorithm is repeated three times until time point t (FIG. 26). At time t (FIG. 26), the triad pole, E;) will be recorded in the upper bits of register 18;); the output pulse from the output of the frequency divider 10 converts trigger 12 into a single state; as a result, the 4QTO will poll the second., third and fourth output of register 18, which corresponds to the 39th, 38th and 37th bits of the register 18 o. Since the signal of the sixth triad is recorded in the sixth triad, units, the Tpiirrep 15 will go to the zero state, and the AND element 5 will close. The logical unit from the second bit of the sixth triad will go to the summing input of the adder 23 and it will be summed up with the contents of the adder 23 (FIG. 26, f, g, k). The content of the adder 23 is converted by a digital-to-analog converter 24 (FIG. 2m). At the output of divider 3, the frequency of the Vits 39-th pulse from the sequence of clock pulses received at its input (Fig. 2c), which arrives at the output of the element OR 8, sets trigger 12 to the zero state (polling of the outputs of the register 18 stops) fig, 2g, and, k, l) and shift the contents of register-18 by one bit, the next pulse is not register 18 by another bit to the next - by one bit

and allow polling the second, third, and fourth output of register 18 (Fig. 2e, g, i, k, l). Since logical zeros are written in the second and third bits of the seventh triad, the state of the adder 23 does not change.

At time tj (Fig.26) in the higher bits of the register 18 will be

0 is recorded in the eighth triad and will begin a survey of the higher bits of register 18 the second, third and fourth outputs of register 18 (Fig. 2g). Since in the first category de eighth

If the triad 5 is written to a logical zero, then the trigger 15 goes into one state (FIG. 2h). Since the third unit of the eighth triad contains a logical unit, it

0 will be subtracted from the contents of the adder 23. Since AND 5 is open, then from its output a clock pulse will pass to the output of the element OR 8, which will terminate. survey (FIG o2zh) and

5 will shift the contents of register 18 by one bit. In view of the fact that in the first category of the ninth, tenth, and eleventh triads a logical zero is written, the operation of the driver will proceed according to the algorithm described above,

The 8th time t (Fig.26) in the higher bits of the register 18 will be recorded the thirteenth triad and its polling will begin (Fig. 2g). Since in the first

The 2nd unit of this triad is recorded as a logical unit, then the trigger 15 is set to the zero state (Fig. 2h). The logical unit recorded in the third digit of the triad is subtracted.

0 from the contents of adder 23 (FIG. 2L, m), At time t-, (FIG. 26), at the output of divider 3 frequencies, a single pulse (39th of the input clock pulses at the input) appears,

5 which will stop polling register 18 and shift its contents by one bit, At time tg (Fig. 26), the next pulse at the output of divider 3 frequencies will move, which will shift

Q contents of register 18 for one more bit. At time tg (fig. 2b), at the output of divider 3 frequencies, another unit impulse is set, which will also shift the contents of register 18 by another bit and cause the appearance of a pulse with divider.

9 frequencies, which indicates that the contents of register 18 has completed a full rewriting cycle and output

1465956

ignal formed. Trigger 4 also

g m 10 p 15 with 20 p p g at 25 h y d d at 30 and in the inlet of one of the second in the in of 40 40 to the right of the 45th then from the cha 50 of the electric of the in of the 55 of the in not ha

will go to the zero state, the voltage of the logical zero from its output (Fig. 26) will close the element And 2, and the voltage of the logical unit from its zero output will prohibit further polling of the bits of the register 18. In this case, the signal conditioner digital code is terminated. For the secondary and more generation of this signal, the algorithm described above is repeated the necessary number of times when a signal is applied to the bus 16. The register bit 18 and the division factors of the dividers 3 and 9 frequencies can be multiples of three and must be equal to or greater than the length of the digital code sequence generated signal. If the sequence length is less than the size of register 18, then it is added by triads of the form 100, which do not affect the pulse shape, but only not. its moment of occurrence. They are added ahead if it is necessary to form a pulse with a certain time delay.

Fig. 3 shows another example of the formation of a signal, with the values of the code triads indicated below the eremin axis.

The proposed signal conditioner provides the formation of an arbitrary waveform with a variable time quantization step.

Claims (1)

Invention Formula An arbitrary waveform generator containing serially connected digital-to-analog converter, an operational amplifier and an output bus, as well as a clock generator and a data bus, which is characterized by the fact that, in order to improve the formation of arbitrary waveforms, by using a variable time quantization step, The first element AND, the first frequency divider, the first trigger, the second element AND, the bus Set zero, the first element OR, the second element OR, the second frequency divider, the third frequency divider, the third element OR, the second trigger the fourth element OR, five ele12 ment 1ish, third trigger, bus start, third element AND, shift register, element NOT, fourth element g, fifth element AND, sixth element AND, data adder, bus Record, the first input of the first element AND connected to the output clock generator, unit output 0 of the first trigger is connected to the second input of the first element I, the output of which is connected to the first input of the second element I and the input of the first frequency divider, output 5 of which is connected to the first input of the second element SH, the second input of which is connected to the output of the second ele - MCiira And, Tue whose input is connected to the output of the third trigger, bus 0, the Zero setting is connected to the first input of the first element OR, the setting input of the shift register and the setting input of the adder, the output of the first element OR connected to the zero input of the first trigger, the setting input of the first frequency divider, the installation input of the third frequency divider, the first input of the fourth element OR 0 and the first input of the fifth OR element, the output of which is connected to the zero input of the third trigger, whose single input is connected to move the fourth AND gate, connected to the bus Start edinichn Im input of the first flip-flop, adjusting input of the second frequency divider and the first input of the third OR gate, the second input of which is connected to the output. 0 of the third frequency divider, and the output is to the single input BTOpoi o trigger, the zero input of which is connected to the output of the fourth IZH element, and the output to the first inputs of the third, 5 fourth, fifth and sixth elements AND, the output of the second element OR is connected to the input the second frequency divider, the input of the third frequency divider, the second input of the fourth. 0 element OR and shifting the input shift register, the output of the second frequency divider is connected to the second input of the first element OR, the first output of the shift register is connected to the 5th input of the shift register, the data inputs of which are bitwise connected to the data bus, the bus is connected to the input of the shift register whose second output is connected to the second input of the third element I and the input of the element NO, the third output of the shift register is connected to the second input of the fifth element Hj and the fourth output to the second input of the sixth element I, whose code is connected to the subtracting input of the adder, the summing input of which is connected to the output The 5th element AND output is connected to the input of the D / A converter, the output of the element is NOT connected to the second input of the fourth element AND, the output of the third element AND is connected to the second input of the fifth element OR, the zero output of the first trigger is connected to the third th input of the fourth element FPI. ") № № ffertff iw fto te tst wi too no wo leo roi rat ets ere o№, act eif eSPageSset ffgt rFk.t 101 rao WI lee