JPH06222786A - Multi digital sound source circuit - Google Patents

Abstract

PURPOSE:To prevent a sound from interfering and to evade such an accident that a transient soundless state occurs even when plural digital signals become opposite phase accidentally by using a time division multiplexer and periodically switching a digital sound source circuit. CONSTITUTION:To the time division multiplexer 5, four outputs from the digital sound sources 2a-2d are inputted, and the outputs from a noise generation circuit 3 and a DAC direct control register 4 are inputted. By the time division multiplexer 5, the inputted six signals and a pause are switched with a clock CLK from a clock generation circuit 8 periodically to be outputted to a D/A converter 6. Thus, no digital signals become zero since no digital signals are addition-processed even when plural digital signals become the opposite phase accidentally, and the digital signals are outputted to a digital/analog conversion circuit respectively independently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-digital sound source circuit in which timbres can be combined, and is improved so as to eliminate interference of sounds output in combination.

[0002]

2. Description of the Related Art Conventionally, analog circuit type mainstream sound source circuits have been used in amusement machines and the like. This kind of analog tone generator circuit has a complicated hardware configuration and is expensive. Therefore, a tone generator circuit based on a digital circuit system (digital tone generator circuit) has been developed, but the tone color cannot be changed because it is fixed by the width of the rectangular wave.

[0003]

Further, when a plurality of digital tone generator circuits having different tones are combined in parallel and digital signals are simply added, the sound of a specific frequency interferes with each other, resulting in a temporary silent state. May be. This is because the rectangular wave of the digital signal output from the multiple digital sound source circuits happens to be in opposite phase at a certain frequency.
It is considered that when these are added together, the sum of the digital signals becomes “0”. The problem of such interference has been an obstacle to the development of the digital tone generator circuit. The present invention has been made in view of the above-mentioned conventional art, and an object thereof is to provide a multi-digital sound source circuit capable of avoiding sound interference.

[0004]

A multi-digital tone generator circuit of the present invention includes a plurality of digital tone generator circuits each capable of outputting a digital signal in which at least one of the number of pulses, a pulse width and a pulse interval during a fixed period is different. A time-division type multiplexer that periodically and sequentially outputs the digital signal output from the digital sound source circuit, and a digital-analog conversion circuit that converts the digital signal output from the time-division type multiplexer into an analog signal. It is characterized by having.

[0005]

According to an external command, the plurality of digital sound source circuits output different digital signals in at least one of the number of pulses, the pulse width and the pulse interval during a certain period, that is, the digital signals having different timbres. In this way, digital signals with different tones are input from these digital sound source circuits to the multiplexer. The time-division multiplexer multiplexes the digital signals output from the plurality of digital sound source circuits in sequence and outputs them to the digital-analog conversion circuit. Therefore, even if a plurality of digital signals happen to have opposite phases, since the digital signals are not added together, they will not become "0" as signals,
Each is independently output to the digital / analog conversion circuit. The digital-analog conversion circuit converts a digital signal from the time division multiplexer into an analog signal. Here, the time-division multiplexer multiplexes digital signals having different timbres at regular intervals at a speed higher than the audibly discriminable speed, so that sounds having different timbres can be heard at the same time.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS. FIG. 1 shows a circuit configuration of a multi-digital sound source circuit 1 according to an embodiment of the present invention. As shown in the figure, the multi-digital sound source circuit 1 of this embodiment has four digital sound source circuits 2a, 2b, 2c and 2d, one noise generating circuit 3, one DAC direct control register 4, a time division type. The multiplexer 5 and the D / A conversion circuit 6 are provided.

Four digital sound source circuits 2a, 2b, 2
The c and 2d are capable of generating 16 kinds of tones and automatically increasing / decreasing the volume according to a command from an external device. Command from the external device for the digital tone generator 2a~2d is held in the buffer register 10 as 8-bit data D ₇ to D _0. Digital sound source circuits 2a to 2d
Has a predetermined number of registers for setting the data, and the internal clock from the clock generation circuit 8
CLK is used to generate different tones. The clock generation circuit 8 divides a clock EXCK of 1 to 16 MHz supplied from an external device into an internal clock CLK of about 0.5 to 1 MHz. The division ratio of the clock generation circuit 8 can be selected from 2 division, 4 division, 8 division, and 16 division. The selection can be performed by setting data in the 2-bit register 9 from the external device through the buffer register 7.

Addresses A ₄ -designating a plurality of registers of the 2-bit register 9 and the digital tone generator circuits 2a-2d
The decoder 10 restores A ₁ and chip enable CE. Digital sound source circuit 2 of this embodiment
A specific example of a to 2d is shown in FIG. The digital sound source circuits 2a to 2d include a frequency dividing circuit 11, a pulse pattern generating circuit 12, an arithmetic circuit 13, a gate circuit 14, and the like.
Two 8-bit registers 15 and 16 for frequency setting, one 8-bit register 17 for pulse pattern setting, one 8-bit register 18 for adding period setting, one 8-bit register 19 for adding value setting, volume One 8-bit register 20 is provided for setting.

Therefore, 8 using the microcomputer
When 12-bit data for frequency setting is input from a bit external device via the buffer register 7, the lower 8 bits of the 12-bit data for frequency setting are registered in the register 15
The upper 4 bits of the register 16 are held in the lower 4 bits of the register 16, and the upper 4 bits of the register 16 are all "0". Similarly, when 4-bit data for pulse pattern setting is input, the 4-bit data for pulse pattern setting is held in the lower 4 bits of the register 17, and the upper 4 bits of the register 17 are all "0". When 1-bit data for setting the additional value is input, the 1-bit data for setting the additional value is held in the fifth and sixth bits from the bottom of the 8-bit register 19 for setting the additional value,
The bit of the other digit of the register 19 becomes "0". The read timing of each register 15 to 20 is synchronized with the clock CLK.

When the clock CLK is input from the clock generating circuit 8, the frequency dividing circuit 11 divides the clock CLK by N and supplies it to the pulse pattern generating circuit 12. Where N is
It is a numerical value of 12-bit data for frequency setting set in the registers 15 and 16. In this embodiment, a 12-bit down counter is used as the frequency dividing circuit 11, and when a numerical value N is set as 12-bit data for frequency setting,
Whenever the counter counts the clock CLK N times and the counter value becomes zero, a pulse having the same width as the clock CLK is output. For example, the value of 12-bit data for frequency setting is N
7 shows the output pulse 11A of the frequency dividing circuit 11 when = 3.
Shown in (a), the output pulse 11A when N = 10 is shown in the same figure (b).
As shown in FIG.
The interval of spreads.

The pulse pattern generation circuit 12 has 16 types shown in FIG. 5 according to the product of the clock CLK and the output pulse 11A of the frequency dividing circuit 11 according to the pulse pattern setting 4-bit data set in the register 17. Pattern 0
Generate any one of F. For example, as shown in the configuration example of the pulse pattern generation circuit 12 in FIG. 3, the pulse pattern generation circuit 12 includes a 16 multiplication circuit 21, three frequency division circuits 22 to 24, and 12 AND circuits 25 to.
36 and a multiplexer 37. Therefore, the output 37A of the multiplexer 37 and the output 11A of the frequency dividing circuit 11 are combined with the AND circuit 36 according to the pulse pattern setting data set in the lower 4 bits of the register 17.
Input to the AND circuit 36, the AND circuit 36 calculates the product and outputs the product as the output 12A of the patterns 0 to F.
Give to. The designation symbols of the pulse patterns 0 to F in FIG. 5 respectively correspond to the values when the 4-bit data for pulse pattern setting is represented in hexadecimal notation.

Thus, the digital tone generator circuit 2 of this embodiment
In a to 2d, the waveform of each pulse output from the frequency dividing circuit 11 can be variably set in a complicated manner as well as a simple change of the duty ratio, and 16 kinds of tone colors can be freely selected.

Every time the arithmetic circuit 13 measures the clock CLK by the numerical value M indicated by the data of the addition cycle set in the register 18, the arithmetic circuit 13 registers the value corresponding to the data D ₄ in the fifth digit from the bottom of the register 19. The volume setting data set to 20 is accumulated and given to the gate circuit 14. In this embodiment the data D ₄ of the register 19 is added to +4 when "1", when the "0" are assumed for adding -4. In addition, the data D _{5 in the} sixth digit from the bottom of the register 19 is “1”.
In the case of, the arithmetic circuit 13 functions, and in the case of "0", the input volume setting data is output as it is.

Output 13 of 8-bit data from the arithmetic circuit 13
A is input to the gate circuit 14 together with the output 12A from the pulse pattern generation circuit 12. The gate circuit 14 is
This is an 8-bit multiplexer that multiplies the output 13A of 8-bit data of the arithmetic circuit 13 and the output 12A of the pulse pattern generation circuit 12, and for example, an equivalent circuit of AND circuits 38 to 45 shown in FIG. 4 can be used.

The output 14A of the gate circuit 14 is an 8-bit digital audio signal and is output to the time division type multiplexer 5. The four outputs 14A from the digital sound source circuits 2a to 2b are input to the time division multiplexer 5, and the outputs from the noise generating circuit 3 and the DAC direct control register 4 are input. Time division type multiplexer 5
Is to periodically switch between the six signals input as shown in FIG. 7 and a pause by the clock CLK from the clock generation circuit 8 and output them to the D / A conversion circuit 6. The noise generator 3 includes a 12-bit oscillation frequency setting unit, an 8-bit attenuator and a random number generating unit, and the oscillation frequency setting unit and the attenuator are used for the digital sound source circuits 2a to 2b. The same one can be used, and the same random number generator as the pulse pattern generating circuit can be used.

A digital signal from a compact disc, a digital audio tape or the like is input to the DAC direct control register 4, and a numerical value can be directly set in the D / A conversion circuit 6. The output signal 1A of the digital tone generator circuit 1 is obtained by converting this into an analog signal by the 8-bit D / A conversion circuit 5. 23 in FIG.
Is an amplifier and 24 is a speaker. D / A conversion circuit 6
Converts the 8-bit digital signal input from the time division multiplexer 5 into an analog signal. This output is
The output signal 1A of the digital sound source circuit 1 is used. Figure 1
Among them, 46 is an amplifier and 47 is a speaker.

The digital sound source circuit 1 described above is formed as a collection circuit. When using the circuit 1, time-series data of the frequency, tone color, and volume of the sound to be generated is created in advance by a personal computer or the like, and the addresses A _{4 to} A _{0 are} generated.
It is sufficient to specify the registers 15 to 20 by using the chip enable CE and sequentially update the data in the corresponding registers. In the above embodiment, the digital sound source circuits 2a ...
The pulse pattern generation circuit 12 and the arithmetic circuit 13 are incorporated in 2d, and the pulse waveform can be changed intricately according to external data to easily variably set the timbre and volume, but the present invention is not limited to this. It is also possible to be able to specify either the tone color or the volume from the outside, instead of the one.

[0018]

As described above in detail with reference to the embodiments, the multi-digital sound source circuit of the present invention uses the time division type multiplexer to switch the digital sound source circuits periodically. Even if a plurality of digital signals happen to have opposite phases, the sounds do not interfere with each other and the temporary silent state can be avoided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a multi-digital tone generator circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of each digital sound source circuit.

FIG. 3 is a diagram showing a configuration example of a pulse pattern generation circuit.

FIG. 4 is a diagram showing a configuration example of a gate circuit.

FIG. 5 is a diagram showing an example of a pulse pattern.

6A and 6B are graphs showing examples of output waveforms of the frequency dividing circuit.

FIG. 7 is a graph showing the periodic output of a time division multiplexer.

[Explanation of symbols]

 1 Multi-Digital Sound Source Circuit 2a to 2d Digital Sound Source Circuit 3 Noise Generation Circuit 4 DAC Direct Control Register 5 Time Division Multiplexer 6 D / A Conversion Circuit 7 Buffer Register 8 Clock Generation Circuit 9 2 Bit Register 10 Decoder 11 Frequency Divider 12 Pulse Pattern generation circuit 13 Operation circuit 14 Gate circuit 15 to 20 register 21 16 Multiplier circuit 22 to 24 2 Frequency divider circuit 25 to 36, 38 to 45 AND circuit 37 Multiplexer 46 Amplifier 47 Speaker

Claims (1)

[Claims] 1. A plurality of digital sound source circuits capable of outputting digital signals different in at least one of the number of pulses, a pulse width, and a pulse interval during a fixed period, and a digital signal output from the digital sound source circuits are periodically arranged. And a digital-analog conversion circuit for converting the digital signal output from the time-division multiplexer into an analog signal.