JPS6232795B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides digital rhythm sounds (percussion sounds).
The present invention relates to a rhythm sound generating device that generates and outputs a rhythm sound.

Generally, conventional rhythm sound generating devices are based on an analog circuit system using transistors, resistors, capacitors, and the like. Then, if a sine wave signal is generated and output at a predetermined period and an envelope is added to it, a sine wave rhythm sound such as a drum sound is generated.Also, if a noise signal is output and an envelope is added to it, a cymbal sound is generated. Noise-based rhythm sounds such as sounds are generated.

By the way, in the case of the above-mentioned conventional rhythm sound generation device, for sine wave rhythm sounds, one independent circuit is provided for each rhythm sound such as claves, high conga, low conga, etc. In the case of noise-based rhythm sounds, one independent circuit is provided for each rhythm sound such as high hats and cymbals. For this reason, the circuit configuration of the rhythm sound generating device has become large-scale. Also, in recent years,
Various attempts have been made to generate rhythm sounds using digital circuits; for example, Japanese Patent Application Laid-Open No. 163595
Such techniques are disclosed in Japanese Patent Application Laid-Open No. 56-24398.

However, in this conventional technology, each rhythm sound is generated by a separate circuit, or requires a fairly large-scale circuit, and furthermore, envelope control is required. However, this was done using traditional analog methods, and there was still room for improvement. In addition, envelope control for scale tones has been studied in various ways, such as in Japanese Patent Application Laid-Open No. 137595/1983, but research has been conducted on what is the optimal configuration for envelope control for rhythm tones. was still insufficient.

The present invention was made against the background of the above-mentioned circumstances, and its purpose is to selectively generate a plurality of types of digital envelope data from an envelope generation circuit by switching the clock cycle, thereby generating a periodic rhythm sound source waveform. It is possible to generate multiple types of rhythm sounds by controlling the envelope of data and noise data.Moreover, it has the simplest configuration in which the envelope is applied to each data, that is, specifically, periodic waveform data. An object of the present invention is to provide a rhythm sound generating device in which pseudo multiplication of envelope data and the data is performed using a shift circuit for noise data and an AND gate circuit group for noise data.

That is, the present application provides a first invention including the above-mentioned basic configuration, and a second invention in which a common envelope is given to the waveform data and noise data by commonly using one envelope data outputted from an envelope data generating means. 2 inventions.

Another feature of the second invention is that only one envelope data generating means is required, which simplifies the overall configuration.

FIG. 1 is a block circuit diagram of this embodiment.
1 in the figure is an oscillator (PG) 1, the output of this oscillator 1 is input to a frequency division counter 2, and the output of this frequency division counter 2 is supplied to a control section 3. A control signal from the CPU 4 is further input to the control unit 3 . This control signal varies depending on the rhythm pattern and the type of rhythm sound.

FIG. 2 shows the details of the main part of this control section 3, and the output of the counter 2 is inputted in 4 bits. That is, of the 4-bit input, the lower bits are A to D. Then, this input signal A is applied to AND gates 31 to 38, and input signal B
is applied to the AND gates 32-34, 36-38, and the input signal C is applied to the AND gates 33, 34, 3.
7 and 38, and input signal D is applied to AND gates 34 and 38.

These AND gates 31 to 38 are further supplied with gate control signals from the CPU 4 via lines 4-1 to 4-8, and the AND gates 3
The outputs of AND gates 1 to 34 are applied to the envelope counter 5 as the envelope clock ES via the OR gate 39, and the outputs of AND gates 35 to 38 are applied to the envelope counter 6 as the envelope clock EN via the OR gate 40. .

Therefore, for example, to make the envelope clock ES the fastest clock, a "1" signal is given as a gate signal from the CPU 4 to the AND gate 31 via the line 4-1. The other lines 4-2 to 4-4 are set to "0" level. Conversely, in order to make the envelope clock ES the slowest clock, a "1" signal is given as a gate signal from the CPU 4 to the AND gate 34 via the line 4-4, and the other AND gates 31 to 33 are provides a "0" signal via lines 4-1 to 4-3.

The envelope clock EN can also be controlled in exactly the same way. Also, if you want to not output noise-type sounds, line 4-5 to 4-8
If the level of is “0”, the envelope clock
ES no longer outputs, and noise-based sounds no longer occur as described below. On the other hand, in order not to output sine wave type sound, line 4-1 to 4-4-
Set the level of 4 to “0” and set the envelope clock.
Do not output EN.

The envelope clocks ES and EN output from the control section 3 are input to envelope counters 5 and 6, respectively.

The envelope counters 5 and 6 generate envelope data for controlling the envelope of the sine wave rhythm sound and the envelope of the noise rhythm sound, respectively, based on the speeds of the envelope clocks ES and EN. Since the envelope counters 5 and 6 are similar, details of the envelope counter 5 will now be explained with reference to FIG. In Figure 3, from CPU4 to line 4-
10, a single "1" signal is supplied at the timing of generating the rhythm sound.

The signal is then applied to a one-shot circuit 60 consisting of a latch 61, an inverter 62, and an AND gate 63. Note that the latch 61 is read by the output A of the frequency dividing counter 2. Therefore, when a "1" signal is supplied from the line 4-9, the one-shot circuit 60 outputs a single "1" signal at the rising edge of the signal and supplies it to the OR gates 64-67. The outputs of the OR gates 64 to 67 are output from the latch 68.
It is latched every time the output A of the frequency division counter 2 is input. The output of this latch 68 is input to a subtracter 69, and its contents are counted down every time the envelope clock ES given from the control section 3 is input, and the contents are counted down to produce 4-bit envelope data.
The signals are supplied to the multiplier 9 as E ₁ to E ₄ .

That is, the output of the latch 68 is applied to the subtracter 69, and the envelope clock ES is applied to the "-1" input terminal via the AND gate 70. Furthermore, the output of an OR gate 71 to which envelope data E ₁ to _{E 4} are supplied is further applied to the AND gate 70 . Therefore, the envelope data E ₁ ~
When E ₄ becomes 0, the above envelope clock ES
is not provided to the subtractor 69.

Then, the output of this subtracter 69 is the output of the OR gate 6
4-67 to latch 68. In this way, the contents of the envelope data _E1 to _E4 will remain the same until the clock ES is input.

Further, the envelope counter 6 has the same configuration as the envelope counter 5 described above, and receives a signal from the CPU 4 via the line 4-9 and an envelope clock from the control section 3.
It operates according to EN and gives the resulting envelope data to the multiplier 7.

The multiplier 7 is supplied with noise data from the noise generation circuit 8, multiplied by the output of the envelope counter 6, and supplied to the adder 11.
Further, the multiplier 9 is supplied with sine wave data from the sine wave generation circuit 10 , multiplied by the output of the envelope counter 5 and supplied to the adder 11 .

Note that the noise generating circuit 8 is configured using, for example, a shift register and an exclusive OR gate,
It is driven by a clock WCK2 of a predetermined frequency given from the frequency division counter 2 via the control section 3 to generate noise data. Further, the sine wave generation circuit 5 stores, for example, a sine wave in the ROM,
It may be read out using a clock having a predetermined frequency, or more simply, a circuit as shown in FIG. 5 may be used. That is, the clock WCK1 from the frequency division counter 2 is applied to the clock input terminal CK of the flip-flop 91 via the control section 3. The set output _Q1 of flip-flop 91 is output from flip-flop 92.
It is applied directly to the clock input terminal CK of the clock, and also applied to an AND gate 93 through an inverter 94, and further applied to an AND gate 95 through an inverter 96. Further, the reset output ₁ of the flip-flop 91 is applied to the input terminal D. Similarly, reset output ₂ of flip-flop 92 is applied to input terminal D. Furthermore, flip-flop 92
The set output _Q2 is given to the AND gate 93 via the inverter 97, and the AND gate 93
The output of is passed through an inverter 98 to an AND gate 95
given to. However, the AND gate 93 output,
The set output Q ₁ of the flip-flop 91 and the output of the AND gate 95 are now the signals W(0) and W, respectively.
(1), W(2). As shown in the time chart of FIG.
The set output Q1 of the flip-flop ₉₂ is inverted at each rising timing, and the set output of the flip-flop 92 is
_Q2 is inverted every time the set output _Q1 of the flip-flop 91 is input to the clock input terminal CK, at each rising timing. Therefore, the above signal W
The output states of (0), W(1), and W(2) are as shown in FIG.
This results in signals whose levels do not overlap with each other. Then, if the signals W(0), W(1), and W(2) are respectively weighted 0 times, 1 times, and 2 times relative to the reference level, the signals W(0), W(1), and W( Depending on the output state of 2), simple step-wave shaped sine wave data can be obtained.
Its period is four times that of clock WCK1.

Multiplier 7 has the configuration shown in FIG. 4, and multiplier 9 has the configuration shown in FIG. 6.

That is, noise data N ₁ to N ₄ are applied to the AND gates 81 to 84 from the noise generation circuit 8,
Envelope data from envelope counter 6
E ₁ to E ₄ are applied. Therefore, if the envelope data is large, the noise data becomes a large output, but as the envelope gradually attenuates, the level of the noise data becomes small.

Further, the multiplier 9 may have a circuit configuration as shown in FIG. That is, this multiplier 9 is connected to the gate circuit group 101
It is made up of. And gate circuit group 10
1 receives the envelope data E ₁ to E ₄ and signals W(0), W(1), and W(2), respectively, and outputs data M ₁ to _{M 5} . As mentioned above, the signal W
(0), W(1), and W(2) are signals whose "1" level does not overlap with each other, so that the signal W(0) is "1".
When the level is input, the gate circuit group 101 is controlled to open and close by this signal W(0), and the data E ₁ to
E ₄ is invalid and all “0” level (GND)
Data M ₁ to _{M 5} are output. That is, data E ₁ ~
_E4 is multiplied by 0 and data _M1 to _M5 are output. Also, if the signal W(1) is input at the “1” level, the data
E ₁ to _{E 4} are the lower 4 bits of data M ₁ to _{M 5} .
The data is output as is to _M1 to _M4 , and the most significant bit data _M5 is set to the "0" level. That is, data E ₁ to _{E 4} are multiplied by 1 to become data M ₁ to _{M 5} . Furthermore, when signal W(2) is input at “1” level, the data
E ₁ to _{E 4} are data of 2 bits or more from data M ₁ to _{M 5}
Output to M ₂ to M ₅ , and also output the least significant bit data M ₁
is set to the "0" level. That is, data E ₁ to _{E 4}
is doubled and output as data _M1 to _M5 . The data M ₁ to _{M 5} are then given to the adder 11 .

On the other hand, the adder 11 adds the outputs of the multipliers 7 and 9, respectively, and sends the result to the DA converter 12, where it is converted into an analog signal and output via an amplifier and a speaker (not shown).

Next, the operation of this embodiment will be explained. Oscillator 1 shown in FIG. 1 generates clock pulses as shown in FIG. 7a, and as a result, frequency dividing counter 2 outputs signals A to D as shown in FIGS. 7b to 7e. Now, for example, among the lines 4-1 to 4-4 from the CPU 4,
When a "1" signal is supplied to the line 4-1 and "0" signals are supplied to the other lines, the control section 3 generates a clock synchronized with this signal A every time the signal A is output from the frequency division counter 2. Now outputs one ES. Then, when a "1" signal is outputted to the envelope counter 5 via the line 4-10, a one-shot signal is outputted from the AND gate 63. As a result,
As shown in FIG. 9b, the envelope data E ₄ to _{E 1} output from the subtracter 69 are sequentially decreased by 1 from 1111 (=15) when the envelope clock ES is output. And the decay rate in this case is signal A
is the same as the output speed of

If a "1" signal is applied only to line 4-2 among the above lines, one clock ES will be output every time the above signal A is output twice. Therefore, in this case, as shown in FIG. 9c, the attenuation speed of the envelope data E ₄ to _{E 1} is 1/2 of that in the case of FIG. 9b.

Similarly, if a "1" signal is given only to line 4-3 or 4-4 among the above lines, clock ES will output one time each time signal A is output 4 or 8 times. . Therefore, in these cases, the attenuation speed of the envelope data _E4 to _E1 is 1/4 or 1/4 of that in the case of FIG. 9b, respectively, as shown in FIG. 9d or 9e, respectively.
It becomes 1/8.

The output state of the envelope clock EN is exactly the same as that of the envelope clock ES, so the output state of the envelope data E ₄ to _{E 1} output from the envelope counter 6 is also the same as the envelope data E ₄ to E from the envelope counter 5. It is the same as the output state of ₁ .

Therefore, in the multiplier 9, when predetermined sine wave data is outputted from the sine wave generation circuit 10 by the operation described later and given to the multiplier 9, the multiplier 9 receives this sine wave data and the envelope counter 5. The envelope data E ₄ to _{E 1} are multiplied by the operation to be described later, and the result is output to the adder 11. However, as mentioned above, since the envelope data E ₄ to _{E 1} are data that attenuate at four types of attenuation speed, the number of types of rhythm sounds emitted from the speakers is determined by the number of types of rhythm sounds emitted from the CPU 4 on the line 4-1 By giving a "1" signal to each of 4-4, four types are obtained. In addition,
As will be described later, the sine wave generation circuit 10 outputs sine wave data with different periods by switching the period of the clock WCK1, so the number of types of rhythm sounds is further multiplied by the number of types of the clock WCK1. For example, if there are two types of clock WCK1, the number of rhythm sounds obtained from the same circuit increases to eight types.

In the sine wave generation circuit 10, a clock is input to the clock input terminal CK of the flip-flop 91 shown in FIG.
Every time WCK1 is input, signals W(0) and W whose "1" level does not overlap each other as shown in FIG.
(1) and W(2) are outputted and given to the multiplier 9 as sine wave data. and signals W(0), W(1), W
The output cycle of (2) is proportional to the output cycle of clock WCK1. In other words, the type of sine wave data is
It changes depending on the output cycle of WCK1.

Next, to specifically explain the operation of the multiplier 9, in FIG. 6, the values of the envelope data _E4 to _E1 input to the gate circuit group 101 are now, for example
1010 (= "10"), when the signal W (0) input to the gate circuit group 101 is "1", the output data (multiplication result data) M ₅ to _{M 1} is 00000.
(=“0”). Further, when the signal W(1) is "1", the data _M5 to _M1 become "01010"(="10"). Furthermore, when the signal W(2) is “1”, the data
M ₅ to _{M 1} are “10100” (= “20”). That is, when the signals W(0), W(1), and W(2) are output, the envelope data _E4 to _E1 are multiplied by 0, 1, and 2, respectively, and output. FIG. 10 shows the output state of the multiplier 9 output (data M ₅ to _{M 1} ). That is, in FIG. 10b, the period of clock WCK1 is as shown in FIG. 10a.
This shows the case of One cycle corresponds to a period in which the clock WCK1 outputs four times.

FIG. 10d shows the output of the multiplier 9 when the clock WCK1 is output at twice the period as in FIG. 10a, as shown in FIG. 10c. In this case as well, stepwise sine wave data similar to FIG. 10b is obtained. The period is therefore twice that of FIG. 10b. In this way, the type of sine wave data changes depending on the period of the clock WCK1.

FIG. 11 shows the state of the multiplier 9 output when the envelope counter 5 output decreases by 1. As shown in the figure, the level of the multiplier 9 output attenuates according to the contents of the envelope data _E4 to _E1 . The rhythm sound emitted from the speaker corresponds to the output of this multiplier 9. In the case of the above example, the number of types of rhythm sounds based on sine wave data is eight, which can be obtained by switching the envelope clock ES and the clock WCK1, respectively.

In the multiplier 7 _, as shown in _FIG .
Multiplication with E ₄ to E ₁ is performed. Now, assuming that the value of the envelope data E ₄ to _{E 1} is 1010 (=10), the AND gates 84 and 82 are open and the AND gates 83 and 81 are closed. Therefore, the multiplier 7 output (data M ₄ to _{M 1} ) is noise data
An envelope is added to N ₄ to N ₁ . In this way, the number of types of rhythm sounds due to noise data can be adjusted using the envelope clock.
By switching EN, four types can be obtained.

and 1 at the same time for lines 4-9 and 4-10
When the oscillation signal is supplied, the multiplier 7 output and the multiplier 9 output are sent to the adder 11 and added, so that the speaker outputs a gradually attenuating rhythm that is a combination of sine wave data and noise data. A sound is emitted. Therefore, the envelope clock
By switching ES, EN, and clock WCK1, a large number of various rhythm sounds can be generated from the same circuit.

Note that in the above embodiment, the envelope clock
There are 4 types of ES and EN, and clock WCK
Although 1 is assumed to be two types, the number of types is arbitrary as long as it is plural.

In addition, in the above embodiment, two envelope counters 5 and 6 are provided so that envelopes can be added independently to sine wave data and noise data, but with one envelope counter, it is possible to add envelopes to both sine wave data and noise data. data may be subjected to envelope control in common, and in that case, a gate circuit may be further added to set the mixing ratio of noise data and sine wave data.

Furthermore, although the above embodiment has been described with reference to the case where one rhythm sound is generated, a plurality of rhythm sounds may be generated simultaneously by time-divisionally operating the circuit shown in FIG. 1. Further, the waveform data is not limited to the above embodiments, and various types such as a slope wave, a square wave, a pulse wave, etc. may be used, and the number of waveform data is arbitrary as long as it is plural.

As explained above, when rhythm sounds are generated by a digital circuit, the envelope data generation means is driven by clocks of different frequencies to generate digital envelope data corresponding to each clock, and these digital envelopes are Based on this, we have provided a rhythm sound generator that generates multiple types of rhythm sounds by performing envelope control on rhythm sound source waveform data such as sine wave data and noise data. Since various rhythm sounds such as , snare drum, and cymbal can be generated, and the rhythm sound generating device can be configured with a digital circuit, it is possible to integrate the system, which has the advantage of being able to significantly reduce the circuit scale. Moreover, according to the present invention, periodic waveform data is multiplied by envelope data in a pseudo manner using a shift circuit, and noise data is multiplied by envelope data in a pseudo manner by a group of AND gate circuits. Since this is done in a digital manner, there is an advantage that the envelope can be applied using a digital circuit with the simplest configuration.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block circuit diagram of this embodiment, FIG. 2 is a detailed diagram of the control section 3 of FIG. 1, and FIG. 3 is a detailed diagram of the envelope counter 5 of FIG. 4 is a detailed diagram of the multiplier 7 in FIG. 1, FIG. 5 is a detailed diagram of the sine wave generation circuit 10 in FIG. 1, FIG. 6 is a detailed diagram of the multiplier 9 in FIG. 1, Figure 7 is a time chart showing the outputs of the oscillator 1 and frequency division counter 2 in Figure 1, Figure 8 is a time chart showing the outputs of the sine wave generating circuit 10 in Figure 5, and Figure 9 is the envelope. Counter 5 output to 4
Figure 10 is a time chart showing the output of the multiplier 9 according to each of the two types of clock WCK1. Figure 11 is a time chart showing the change in the output of the envelope counter 5 and the corresponding change in the output of the multiplier 9. It's a chat. 3... Control unit, 4... CPU, 5, 6... Envelope counter, 7, 9... Multiplier, 8... Noise generation circuit, 10... Sine wave generation circuit, 11
... Adder, 12 ... D-A converter.

Claims (1)

[Scope of Claims] 1. Rhythm sound source waveform data generation means for generating digital rhythm sound source waveform data representing a periodic signal having a predetermined frequency; Noise data generation means for generating digital noise data; and a plurality of types having different frequencies. clock selection output means for selectively outputting the clock of the clock; and first envelope data generation means for generating digital envelope data for the digital rhythm sound source waveform data driven by the first clock selectively output from the clock selection output means. and second envelope data generation means for generating digital envelope data for the digital noise data, driven by a second clock selectively output from the clock selection output means; The shift circuit includes a shift circuit for performing digital multiplication by shifting the digital envelope data output from the rhythm sound source waveform data generating means according to the value of the digital rhythm sound source waveform data output from the rhythm sound source waveform data generating means, and Each bit signal of the digital envelope data output from the first envelope control means for obtaining controlled digital rhythm sound source waveform data and the second envelope data generation means is input to one side, and the noise data generation means a second envelope control means including a group of AND gate circuits to which each bit signal of the digital noise data outputted from the circuit is inputted, and is adapted to obtain envelope-controlled digital noise data from the group of AND gate circuits; The envelope-controlled digital rhythm sound source waveform data output from the first envelope control means and the envelope-controlled digital noise data output from the second envelope control means are combined and output as digital rhythm sound data. A rhythm sound generating device characterized by comprising: a synthesis means for generating a rhythm sound; 2. The rhythm sound generating device according to claim 1, wherein the first and second envelope data generating means each generate digital envelope data representing an attenuation envelope. 3. The rhythm sound source waveform data generation means includes a selection means for selecting one clock from a plurality of types of clocks having different frequencies, and is driven by the clock selected by the selection means and has a frequency corresponding to the clock. 2. The rhythm sound generating device according to claim 1, further comprising waveform data output means for outputting said digital rhythm sound source waveform data representing a periodic signal. 4 Rhythm sound source waveform data generation means for generating digital rhythm sound source waveform data representing a periodic signal having a predetermined frequency, noise data generation means for generating digital noise data, and selectively outputting multiple types of clocks with different frequencies. A clock selection output means; Driven by a clock selectively output from the clock selection output means, one piece of digital envelope data is generated for common envelope control of the digital rhythm sound source waveform data and the digital noise data. envelope data generating means for generating digital rhythm data; and digitally multiplying the digital envelope data outputted from the envelope data generating means by performing a shift process according to the value of the digital rhythm sound source waveform data outputted from the rhythm sound source waveform data generating means. a first envelope control means including a shift circuit for performing a shift process, and configured to obtain envelope-controlled digital rhythm sound source waveform data through shift processing by the shift circuit; It includes a group of AND gate circuits in which each bit signal is input as one input, and each bit signal of the digital noise data outputted from the noise data generating means is input as the other input, and the envelope-controlled digital signal is output from the AND gate circuit group. a second envelope control means configured to obtain noise data; the envelope-controlled digital rhythm sound source waveform data output from the first envelope control means; and the envelope-controlled digital rhythm sound source waveform data output from the second envelope control means. A rhythm sound generation device comprising: a synthesis means for synthesizing digital noise data and outputting the synthesized data as digital rhythm sound data. 5. The rhythm sound generating device according to claim 4, wherein the envelope data generating means generates digital envelope data representing an attenuation envelope. 6. The rhythm sound source waveform data generation means includes a selection means for selecting one clock from a plurality of types of clocks having different frequencies, and is driven by the clock selected by the selection means and has a frequency corresponding to the clock. 5. The rhythm sound generating device according to claim 4, further comprising waveform data output means for outputting said digital rhythm sound source waveform data representing a periodic signal.