JPH05121463A - Assembly structure of semiconductor device - Google Patents

Abstract

PURPOSE:To properly perform a solder bonding operation by a method wherein, when a semiconductor chip is solder-mounted on an electrode substrate via a spacer, the misalignment of the components is restrained. CONSTITUTION:In a semiconductor device wherein a semiconductor chip 2 is solder-mounted on an electrode substrate 1 via a spacer and its peripheral region is resin-sealed. In the semiconductor device, an integrated spacer 7 in which preliminary solder layers 7b, 7c have been formed on both faces of a base material 7a is used as the spacer, and the integrated spacer, the semiconductor chip 2 and a lead 3 are stacked on the electrode substrate are reflow-soldered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device assembly structure for a planar diode or the like.

[0002]

2. Description of the Related Art First, FIG. 4 shows the structure of a head semiconductor device assembled by a conventional method. In the figure, 1 is an electrode substrate (metal frame) 2, a semiconductor chip, 2a is a passivation film formed on the lower surface side of the semiconductor chip 2, 3 is a lead soldered to the upper surface of the semiconductor chip 2, and 4 is the electrode substrate 1 and the semiconductor. Spacers 5 interposed between the chips 2 and joined by soldering are solder sheets, and 6 is a sealing resin layer. The spacer 4 is provided to secure a required insulation distance between the electrode substrate 1 and the passivation film 2a of the semiconductor chip 2 facing the electrode substrate 1.

The semiconductor device having such a structure is assembled and configured as follows. First, spacers 4, semiconductor chips 2, leads 3 and solder sheets 5 are alternately stacked and placed on the electrode substrate 1, and then heat is applied from a heat source such as a heating furnace to form the electrode substrate 1, spacers 4, semiconductors. After reflow soldering between the chips 2 and the leads 3, the peripheral region of the semiconductor chip 1 is sealed with resin to complete the process.

[0004]

In the semiconductor device having the above structure, the electrode substrate 1, the semiconductor chip 2, the spacer 4 and the solder sheet 5 can be freely moved during the reflow soldering step. Therefore, when the solder sheet 5 is melted, there are many cases where the respective parts are joined while being relatively displaced from the predetermined assembly position as illustrated. In addition, if the soldering position is displaced as described above, the passivation film 2a
A desired insulation distance cannot be ensured between them and causes insulation failure. Incidentally, in the past, the rate of occurrence of such insulation defective products has reached about 6% of the production amount, and therefore there is a strong demand for an improvement measure for improving the non-defective product rate.

The present invention has been made in view of the above points, and an object thereof is to improve a part of parts to
An object of the present invention is to provide an assembly structure of a semiconductor device which solves the above-mentioned problems and can appropriately solder-bond components to each other without displacement.

[0006]

In order to achieve the above object, the present invention provides a semiconductor device in which a semiconductor chip is solder-mounted on an electrode substrate with a spacer interposed and a peripheral region thereof is resin-sealed. The spacers are assembled and configured by using integral spacers having preliminary solder layers provided on both surfaces of the base material. Further, as an embodiment of the above configuration, there is a configuration in which a spacer positioning recess is provided in the central portion of the plate surface of the electrode substrate.

[0007]

According to the above structure, since the preliminary solder layer integrated with the base material of the spacer is formed on both surfaces of the spacer, the electrode substrate and the spacer,
No extreme misalignment occurs between the spacer and the semiconductor chip, which improves the yield rate of products. In addition, by providing a recess for positioning in which the bottom of the spacer fits in the plate surface of the electrode substrate in advance,
During assembly, the spacers are held in place with respect to the electrode substrate. Therefore, it is possible to more reliably prevent the positional displacement between the components in the subsequent soldering process. In addition,
In the soldering process, higher assembly accuracy can be obtained by using an assembly jig that constrains each component stacked and placed on the electrode substrate at a predetermined position and presses it from above.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings of the embodiments, the same parts corresponding to those in FIG. 4 are designated by the same reference numerals. First, in FIGS. 1 and 2, as a spacer interposed between the electrode substrate 1 and the semiconductor chip 2, a preliminary solder layer 7 is previously formed on both upper and lower surfaces of a spacer base material 7a such as a metal plate or a low resistance Si plate.
The semiconductor device is assembled as follows by using the integral spacer 7 formed by forming b and 7c.

That is, as shown in FIG. 2, the integral spacer 7, the semiconductor chip 2 and the lead 3 are sequentially stacked on the electrode substrate 1 and placed at a fixed position.
The pot-shaped assembling jig 8 is placed on top of the above and pressure is applied from above, and reflow soldering is performed in this state. After the semiconductor chip 2 is solder-mounted on the electrode substrate 1 in this manner, the sealing resin layer 6 is formed on the peripheral region of the semiconductor chip 2 as in FIG.
To mold.

When the product manufactured according to the present invention and the conventional product were compared and inspected, it was found that in the conventional product, the displacement of the spacer 4 with respect to the electrode substrate 1 was up to about 6 mm. The product has a maximum of 2 mm or less, which results in an insulation failure rate of 6% of the conventional level.
It has been confirmed that the yield of the products is significantly improved by reducing the above to 0.5% or less.

FIG. 3 shows an applied embodiment of the present invention, in which the integral spacer 7 is provided at the center of the upper surface of the electrode substrate 1.
The shallow concave portion 1a having a depth corresponding to the outer shape of is formed in advance. Then, when assembling the semiconductor device, the recessed portion 1a is used as a positioning recessed portion, and the spacer 7 is fitted into the recessed portion 1a for positioning and holding. With such a configuration, the spacer 7 is restrained and held at a predetermined position with respect to the electrode substrate 1, and it is possible to reliably prevent positional displacement between components during subsequent reflow soldering.

[0012]

As described above, according to the assembly structure of the present invention, in the soldering step of solder-mounting the semiconductor chip on the electrode substrate, the positional displacement of the electrode substrate, the spacer and the semiconductor chip can be favorably generated. This can be prevented, whereby a required insulation distance can be secured between the passivation film of the semiconductor chip and the yield rate of products can be significantly increased.

[Brief description of drawings]

FIG. 1 is an assembly configuration diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a solder mounting process in the configuration of FIG.

FIG. 3 is an assembly configuration diagram of a semiconductor device showing an application example of the present invention.

FIG. 4 is an assembly configuration diagram of a semiconductor device manufactured by a conventional assembly method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electrode substrate 2 Semiconductor chip 3 Lead 6 Encapsulating resin layer 7 Integrated spacer 7a Spacer base material 7b Pre-solder layer 7c Pre-solder layer

Claims (3)

[Claims] 1. A semiconductor device in which a semiconductor chip is solder-mounted with an intervening spacer on an electrode substrate, and a peripheral region thereof is resin-sealed, and an integrated spacer having a pre-solder layer on both surfaces thereof is used as the spacer. A semiconductor device assembling structure characterized by being assembled by using. 2. The assembly structure for a semiconductor device according to claim 1, wherein a positioning recess for spacers is provided in the center of the plate surface of the electrode substrate. 3. The assembly structure according to claim 1, wherein the semiconductor chip is a planar type element.