CN112310016A - Low stress asymmetric two-sided module - Google Patents

Low stress asymmetric two-sided module Download PDF

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Publication number
CN112310016A
CN112310016A CN202010758504.5A CN202010758504A CN112310016A CN 112310016 A CN112310016 A CN 112310016A CN 202010758504 A CN202010758504 A CN 202010758504A CN 112310016 A CN112310016 A CN 112310016A
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China
Prior art keywords
substrate
coupled
substrates
dies
spacers
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CN202010758504.5A
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Chinese (zh)
Inventor
周志雄
A·普拉扎卡莫
S·圣日尔曼
林育圣
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Priority claimed from US16/678,039 external-priority patent/US11462515B2/en
Priority claimed from US16/733,322 external-priority patent/US11469163B2/en
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN112310016A publication Critical patent/CN112310016A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

The invention provides a low stress asymmetric double-sided module. Embodiments of a semiconductor package may include: a first substrate having two or more dies coupled to a first side; a clamp coupled to each of two or more dies on the first substrate; and a second substrate having two or more dies coupled to a first side of the second substrate. A clip may be coupled to each of the two or more dies on the second substrate. The package may include: two or more spacers coupled to a first side of the first substrate; and a lead frame between the first substrate and the second substrate; and a molding compound. The second side of each of the first substrate and the second substrate may be exposed through the molding compound. When coupled by the two or more spacers, the perimeter of the first substrate and the perimeter of the second substrate may not completely overlap.

Description

Low stress asymmetric two-sided module
Cross Reference to Related Applications
The present application claims benefit of the filing date of U.S. provisional patent application 62/882,119 entitled "LOW stress asymmetric double sided MODULE (LOW STRESS ASYMMETRIC DUAL SIDE MODULE)" to Chew et al, filed on 2019, 8/2, the disclosure of which is hereby incorporated by reference in its entirety.
Technical Field
Aspects of the present document generally relate to modular semiconductor packages, such as power semiconductor packages with double-sided cooling capability. More particular embodiments relate to lead frames.
Background
Power semiconductor packages typically include a plurality of stacked substrates. A heat sink may be coupled to external terminals of the device. Some power semiconductor packages may include a heat spreader having a fin array structure.
Disclosure of Invention
Embodiments of a semiconductor package may include: a first substrate having two or more dies coupled to a first side of the first substrate. A clip may be coupled to each of the two or more dies on the first substrate. The package may also include a second substrate having two or more dies coupled to a first side of the second substrate. A clip may be coupled to each of the two or more dies on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate. The package may further include: a lead frame between the first substrate and the second substrate; and a molding compound (molding compound) encapsulating the leadframe. The second side of each of the first substrate and the second substrate may be exposed through the molding compound. When coupled by the two or more spacers, the perimeter of the first substrate and the perimeter of the second substrate may not completely overlap.
Embodiments of the semiconductor package may include one, all, or any of the following:
the two or more dies may include an Insulated Gate Bipolar Transistor (IGBT) die and a Fast Recovery Die (FRD).
The first and second substrates may include a direct bond copper substrate (DBC) having a doping with zirconium dioxide (ZrO)2) Alumina (Al)2O3) Ceramic, silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high strength AlN (H-AlN) ceramic, or any combination thereof.
The semiconductor package may also include a heat spreader coupled with the second side of the first die, the second side of the second die, or any combination thereof.
The two or more spacers may be made of a conductive material and may electrically couple the first substrate to the second substrate.
The first substrate and the second substrate may include a direct bonded copper substrate (DBC), an Insulated Metal Substrate Technology (IMST) substrate, an Active Metal Bonded (AMB) substrate, or any combination thereof.
Embodiments of a semiconductor package may include: a lead frame; and a first substrate mechanically and electrically coupled to the first side of the leadframe. The first substrate may include two or more dies on a first side of the first substrate. A clip may be coupled to each of the two or more dies coupled to the first side of the first substrate. The package may also include a second substrate mechanically and electrically coupled to the second side of the leadframe. The second substrate may include two or more dies on a first side of the second substrate, and a clip is coupled to each of the two or more dies. The package may also include two or more spacers coupled to the first side of each of the first and second substrates. A molding compound may encapsulate the first and second sides of the leadframe. The first side of the first substrate and the first side of the second substrate may be asymmetrically coupled through the two or more spacers.
Embodiments of the semiconductor package may include one, all, or any of the following:
the two or more dies may include an Insulated Gate Bipolar Transistor (IGBT) die and a Fast Recovery Die (FRD).
The first and second substrates may include a direct bond copper substrate (DBC) having a doping with zirconium dioxide (ZrO)2) Alumina (Al)2O3) Ceramic, silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high strength AlN (H-AlN) ceramic, or any combination thereof.
The package may also include a heat spreader coupled with one of the second side of the first die, the second side of the second die, or any combination thereof.
The two or more spacers may be made of a conductive material and electrically couple the first substrate to the second substrate.
The first substrate and the second substrate may include a direct bonded copper substrate (DBC), an Insulated Metal Substrate Technology (IMST) substrate, an Active Metal Bonded (AMB) substrate, or any combination thereof.
Embodiments of the semiconductor package may be fabricated by a method of forming a semiconductor package. Various method embodiments may include: a first panel of a first substrate and a second panel of a second substrate are provided. The method may also include printing a first conductive bonding material on the first side of the first panel of substrates and the second side of the first panel of substrates in a predetermined location, and coupling two or more dies to each substrate of the first panel of substrates and to each substrate of the second panel of substrates at the predetermined location. The method may also include dispensing a second conductive material onto the second side of each of the two or more dies, and coupling a clip to each of the two or more dies. The method may include cutting (singulating) each of the first and second panels into a plurality of first and second substrates, respectively. The method may include dispensing solder onto a plurality of predetermined locations on the first side of each of the plurality of first substrates and each of the plurality of second substrates. The method may also include coupling a first substrate of the plurality of first substrates to a first side of a leadframe, and coupling two or more spacers to the first side of the first substrate. The method may also include coupling a first side of a second substrate of the plurality of second substrates to the two or more spacers and to a second side of the leadframe.
Embodiments of the method of forming a semiconductor package may include one, all, or any of the following:
the method may also include trimming the lead frame to expose a plurality of leads and forming the leads.
The method may also include encapsulating the leadframe on the first side and the second side, wherein the second side of each of the plurality of first substrates and the plurality of second substrates is exposed.
The first panel of the first substrate and the second panel of the second substrate may each comprise a direct bond copper substrate (DBC), an Insulated Metal Substrate Technology (IMST) substrate, an Active Metal Bond (AMB) substrate, or any combination thereof.
The method may also include coupling a heat spreader to one of the second side of the first die, the second side of the second die, or any combination thereof.
The method may also include coupling a heat spreader to the second side of the first substrate of the plurality of first substrates, the second side of the second substrate of the plurality of second substrates, or any combination thereof.
The two or more spacers may be made of a conductive material and may electrically couple the first substrate to the second substrate.
The first side of the first substrate and the first side of the second substrate may be asymmetrically coupled through the two or more spacers.
The first conductive material and the second conductive material may include a solder paste or a sintering paste.
The above and other aspects, features and advantages will be apparent to one of ordinary skill in the art from the specification and drawings, and from the claims.
Drawings
Embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and:
fig. 1 is a side view of an embodiment of a semiconductor package;
FIG. 2 is a top perspective view of an embodiment of a semiconductor package;
FIG. 3 is a top perspective view of an embodiment of a lead frame prior to coupling a second substrate to the lead frame;
FIG. 4 is a top perspective view of an embodiment of a first substrate;
FIG. 5 is a top perspective view of an embodiment of a second substrate;
FIG. 6 is a top perspective view of an embodiment of a panel of substrates;
FIG. 7 is a top perspective view of an embodiment of a panel having a substrate of conductive material coupled in predetermined locations;
FIG. 8 is a top perspective view of an embodiment of a panel having a substrate with two dies coupled to predetermined locations;
FIG. 9 is a top perspective view of an embodiment of a conductive material coupled to each of two dies;
FIG. 10 is a top perspective view of an embodiment of two clips coupled to each of two dies;
FIG. 11 is a top perspective view of an embodiment of a clamp;
FIG. 12 is a top perspective view of an embodiment of wire bonds coupled to two dies;
FIG. 13 is a top perspective view of an embodiment of a panel of substrates cut into three substrates;
FIG. 14 is a top perspective view of an embodiment of a first substrate after dicing;
FIG. 15 is a top perspective view of an embodiment of a second substrate after dicing;
FIG. 16 is a top perspective view of an embodiment of a first substrate coupled to a lead frame and a second substrate prior to being coupled to the lead frame;
FIG. 17 is a close-up view of an embodiment of a spacer;
FIG. 18 is a top perspective view of an embodiment of the second side of the leadframe after a second substrate is coupled to the leadframe;
FIG. 19 is a top perspective view of an embodiment of a first side of a lead frame;
figure 20 is a side view of an embodiment of a semiconductor package;
FIG. 21 is a top view of an embodiment of a semiconductor package after encapsulation; and
fig. 22 is a perspective view of an embodiment of a semiconductor package after wire trimming and formation.
Detailed Description
The present disclosure, aspects, and embodiments thereof, are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly procedures, and/or method elements known in the art to be compatible with the intended semiconductor package will be readily capable of use with the specific embodiments of the present disclosure. Thus, for example, although specific embodiments are disclosed herein, such embodiments and implementation components may include any shape, size, style, type, model, version, measure, concentration, material, quantity, method element, step, and/or the like known in the art for such semiconductor packages and implementation components and methods consistent with the intended operation and method.
Referring to fig. 1, a side view of an embodiment of a semiconductor package 2 is shown. As shown, the semiconductor package includes a first substrate 4 coupled to a first side 6 of a lead frame 8. The first substrate 4 includes two dies 10 and 12 that are coupled to the first substrate 4 in two predetermined locations. In various embodiments, more than two dies may be coupled to the first substrate. As non-limiting examples, the die may include an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Die (FRD), any other semiconductor die, or any combination thereof. The semiconductor package also includes a second substrate 14 coupled to a second side 16 of the leadframe 8. The lead frame 8 is coupled between the first substrate 4 and the second substrate 14. The second substrate has two dies coupled to two predetermined locations on a first side of the second substrate. In various embodiments, the two dies coupled to the second substrate may include Insulated Gate Bipolar Transistors (IGBTs), Fast Recovery Dies (FRDs), any other semiconductor die, or any combination thereof, as non-limiting examples.
Each of the first and second substrates shown in fig. 1 is a direct bonded copper substrate (DBC) comprising a ceramic substrate, wherein a copper plate is coupled to a first and second side of the ceramic substrate. In various embodiments, the DBC may comprise a material doped with zirconium dioxide (ZrO)2) Alumina (Al)2O3) Ceramic (HPS). In other embodiments, the ceramic may be made of other materials, such as a silicon nitride (Si3N4) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof. In some embodiments, the thickness of each layer of the Cu/HPS/Cu DBC substrate may include 0.30mm Cu, 0.32mm ceramic/HPS, and 0.30mm Cu. In other embodiments, the thickness may be varied based on electrical requirements, thermal requirements, package height control, and other parameters of the device. In other embodiments, the first substrate, the second substrate, or both the first substrate and the second substrate may be made of another substrate material, such as, by way of non-limiting example, an Active Metal Brazing (AMB) substrate, an insulating substrate, or a combination thereofMetal Substrate Technology (IMST), laminated substrates, substrates having a metal layer on only one surface of the substrate, any combination thereof, and any other substrate type.
Referring to fig. 2, a top view of an embodiment of a semiconductor package 22 is shown. In this view, the second side 24 of the leadframe is shown with a second substrate 28 coupled thereto. The second substrate 28 may be coupled to the lead frame 24 by leads 30 formed in an upward position. As shown, the first substrate 32 is coupled to a first side of the leadframe opposite the second substrate. A portion of the first side of the first substrate faces a portion but not all of the first side of the second substrate. Additionally, as shown, the perimeter of the first substrate and the perimeter of the second substrate do not completely overlap when coupled to the lead frame and the spacer. The first substrate and the second substrate are thus asymmetrically coupled to the lead frame.
Referring to fig. 3, an embodiment of a lead frame 34 is shown. The lead frame may be formed by stamping the leads to offset contact with the first and second substrates. A first substrate 40 is coupled to a first side of the leadframe 34 by leads 36 and wire bonds 38. In various embodiments, the leadframe may be coupled to the first substrate by other conductive materials (such as solder or die attach materials). The first substrate includes two clamps 42 and 44 coupled to a first side of the first substrate by a conductive bonding material. In various embodiments, the conductive bonding material may include, by way of non-limiting example, a lead (Pb) -free solder paste, a sintered silver paste, other conductive bonding materials, or any combination thereof. The two spacers 42 and 44 may be formed of one or more conductive materials and may provide electrical contact between the first and second substrates. In various embodiments, the spacers may be formed of copper or a copper alloy.
As shown in fig. 3, a first side of a second substrate 46 is coupled to the device by leads on the lead frame and by two spacers 42 and 44, as indicated by dashed lines 48 and 50. The second substrate includes two semiconductor dies 52 and 54 coupled to the first side of the substrate by a conductive material. In various embodiments, the two dies may include IGBTs, FRDs, or any other die described herein. A clip 56 is coupled to a first side of each of the two dies. In various embodiments, the clamp may have a thickness of about 0.3 mm. In other embodiments, the thickness of the clamp may vary based on electrical requirements, thermal requirements, or other design parameters of the device. In various embodiments, the clip may be formed of copper or a copper alloy.
Referring to fig. 4, an embodiment of a first substrate 60 is shown. In various embodiments, the first substrate may comprise a direct bond copper substrate. In various embodiments, the thickness of each layer of the substrate may be about 0.30mm of Cu, about 0.32mm of ceramic, and about 0.30mm of Cu. In some embodiments, the thickness of each layer may differ based on the parameters/structure of the device. The first substrate 60 includes a first die 62 coupled to a first side 65 of the substrate. A clip 64 is coupled to a first side of the first die 62. In various embodiments, the first die may be an FRD die. As shown, the first substrate 60 also includes a second die 66 coupled to the first side 65 of the first substrate 60. In some embodiments, the second die may include an IGBT die. Clip 68 is coupled to the first side of second die 66 by a conductive material. In various embodiments, the clip may be formed of copper, a copper alloy, or another conductive material.
Referring to fig. 5, an embodiment of a second substrate 70 is shown. In various embodiments, the second substrate may comprise a Directly Bonded Copper (DBC) substrate. In some embodiments, the DBC may comprise a material doped with zirconium dioxide (ZrO)2) Or any other combination of alumina (Al) as described herein2O3) A ceramic. The second substrate 70 includes a first die 72 coupled to a first side 74 of the substrate. In various embodiments, the first die may be an FRD die. As shown, a clip 76 is coupled to a first side of the first die 72. In various embodiments, the clip may be formed of copper, a copper alloy, or any other material described herein for the clip. In various embodiments, the clamp may have a thickness of about 0.3 mm. In other embodiments, the thickness of the clamp may be based on the electrical and thermal requirements of the deviceLarger or smaller. As shown, the second substrate 70 also includes a second die 78 coupled to the first side 74 of the first substrate 70. In some embodiments, the second die may include an IGBT die. Clip 80 is coupled to the first side of second die 78 by a conductive material. In various embodiments, the conductive material coupling the clip to the die may be a high temperature solder or a high temperature sintering paste. The solder and sintering paste may comprise any of the die bonding or electrical coupling material types described herein. When comparing the first substrate 60 of fig. 4 with the second substrate 70 of fig. 5, it should be noted that the grippers have different orientations on each substrate. This difference in orientation can help offset the substrate when it is coupled to the leadframe.
Semiconductor packages as described herein may be fabricated by various embodiments of methods of forming semiconductor packages. The method may include providing a panel of first substrates. The method may include a Modular Subassembly (MSA) in the form of a panel comprising two sets of panels: a first panel of a first substrate and a second panel of a second substrate. Referring to fig. 6, a plurality of panels 82 of first substrate 84 are shown. The method may also include providing a plurality of panels of the second substrate. For ease of illustration, only the face plate of the first substrate is shown, although the method of making the face plate of the second substrate is similar. Referring again to fig. 4 and 5, the first substrate 60 and the second substrate 70 do have slightly different orientations and positions when the clamps are coupled and the conductive material is coupled to the first side of each substrate. Each of the first substrate and the second substrate may include a DBC substrate. In various embodiments, the initial thickness of each of the layers of the substrate may include about 0.30mm of Cu, about 0.32mm of ceramic, and about 0.30mm of Cu. In some embodiments, the ceramic layer may include doped ZrO2Al of (2)2O3A ceramic. In other embodiments, the ceramic layer may include a silicon nitride (Si3N4) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof. In still other embodiments, the first and second substrates may comprise Insulated Metal Substrate Technology (IMST), Active Metal Brazing (AMB) substrates, or any other substrate mentioned herein.
The method may also include printing a first conductive bonding material on the first side of each of the first panel of the substrate and the second panel of the substrate in a predetermined location. In various embodiments, the conductive material may include a high temperature solder or a high temperature sintering paste. In some embodiments, the solder may be a lead-free solder, such as SnAg including 96.5% tin (Sn) and 3.5% silver (Ag)3.5Or SAC305 including 96.5% Sn, 3% Ag, and 0.5% copper (Cu). In other embodiments, the conductive bonding material may include a sintered silver paste. Referring to fig. 7, a first panel of substrates 82 is shown after coupling conductive material 85 in predetermined locations 86 to each of a plurality of first substrates 88.
The method may also include coupling two or more dies to each of the first panel of substrates and the second panel of substrates. Two or more dies may be coupled to the substrate in predetermined locations of the conductive bonding material. In various embodiments, the die may include an IGBT, an FRD, or any other semiconductor die described herein. Referring to fig. 8, panel 82 of substrate 84 is shown after coupling two dies 90 and 92 to each of two predetermined locations 86 and 88. The method may also include dispensing a second conductive material onto a second side or exposed surface of each of the two or more dies. In various embodiments, the second conductive material may be the same material printed onto the first side of the substrate or any other conductive material disclosed in this document. Referring to fig. 9, panel 82 of substrate 84 is shown after dispensing a second conductive material 94 onto the second side of each of the two dies 90 and 92.
The method may also include coupling a clip to each of the two or more dies through the second conductive material. In some embodiments, the fixture may be coupled to the die by pressure sintering. Referring to fig. 10, panel 82 of substrate 84 is shown after clips 96 and 98 have been coupled to dies 90 and 92 by a conductive material. Various embodiments of such methods may allow for uniform pressure to be applied to the substrate as the clip is installed prior to assembly in the semiconductor package. As shown, the clip is placed perpendicular to the leads of the leadframe. Referring to fig. 11, an embodiment of a clamp is shown. In various embodiments, the clamp may have a thickness of about 0.3mm, but in other embodiments, the thickness of the clamp may be greater or less based on the electrical or thermal requirements of the device. In various embodiments of similarly sized dies, the clip may be flexible, which may reduce stress on the die. In some embodiments, the clip may be formed of copper or a copper alloy.
The method may also include reflowing the solder or sinter paste and flux cleaning the surface of the substrate. The method may then include electrically coupling two or more dies to each of the plurality of first substrates and the plurality of second substrates. As shown in fig. 12, the die 90 may be coupled to the substrate 88 by wire bonds 102. In various embodiments, the wire bonds may be formed from aluminum or other conductive materials. While the use of wire bonds is shown in fig. 12, in other embodiments, other electrical connectors may be used to connect the clamps, such as bumps, stud bumps, posts, or any other electrical connector type, as non-limiting examples.
The method may also include cutting each of the first panel of substrates and the second panel of substrates into a plurality of first substrates and second substrates. In various implementations, a panel of substrates may have a scribe line between each of the plurality of substrates (or may be first scored using a stylus to form such a line), and the substrates may be cut by breaking at the scribe lines. In other embodiments, the plurality of substrates may be cut by laser cutting. In yet other embodiments, the panel may be cut into multiple substrates by sawing. Referring to fig. 13, panel 82 is shown after some of a plurality of substrates 84 have been cut from the panel. In various embodiments, each of the substrates may be probe tested before or after dicing and before coupling the substrates to the lead frame.
The method may also include dispensing solder onto a plurality of predetermined locations on the first side of each of the first substrate and the second substrate. In various embodiments, the solder may be a low temperature solder. Referring to fig. 14 and 15, each of the first substrate 104 and the second substrate 106 is shown after dispensing solder in the predetermined location 108. The method may also include coupling a first substrate to a first side of the leadframe. The first side of the first substrate may be coupled to the lead frame by solder at a predetermined location. Leads coupled with the first substrate may be formed toward the first side of the leadframe. Referring to fig. 16, the leadframe is shown after coupling the first substrate 104 to a first side of the leadframe 110.
The method may also include coupling two or more spacers to the first side of the first substrate at predetermined locations not coupled to the lead frame. The clip may be formed of a conductive material. The spacers may electrically couple the first substrate to the second substrate. Because the first and second substrates are coupled only by the spacers, there may be less stress on the components of the semiconductor package during assembly, reflow, and other manufacturing processing steps. Still referring to fig. 16, two spacers 112 are shown coupled to the first side of the first substrate 104 by solder. Fig. 17 shows an enlarged view of the spacer 112. In various embodiments, the spacers may be formed of a conductive material (such as copper). The method also includes coupling a first side of the second substrate 106 to the two spacers and to a second side of the leadframe, as indicated by dashed line 114 in fig. 16. Leads coupled to the second substrate are formed toward the second side of the leadframe.
Referring to fig. 18, an embodiment of the semiconductor package 116 is shown after coupling the first side of the second substrate 106 to two spacers and to the second side of the leadframe 110. As shown, the first side of the first substrate and the first side of the second substrate are asymmetrically coupled by two spacers. Such a configuration may place less stress on the internal components of the package. Referring to fig. 19, a first side of the lead frame 110 is shown. In this view, the second side 118 of the first substrate 104 and the first side of the second substrate 106 are visible. The second side of each of the first and second substrates is exposed to act as a heat spreader for the semiconductor package.
Referring to fig. 20, a side view of the semiconductor package 120 is shown. In this view, the leadframe 122 is shown having a first substrate 124 coupled to a first side of the leadframe 122 and a second substrate 126 coupled to a second side of the leadframe 122. First substrate 124 and second substrate 126 are mechanically and electrically coupled to leadframe 122 by leads 128 formed toward the respective substrates. The first substrate 124 has two dies 130 and 132 coupled to a first side of the first substrate 124. Clips 134 and 136 are coupled to each of the two dies 130 and 132. The structure of the semiconductor package allows the clip to be vertically coupled with the leads of the lead frame.
The semiconductor package also includes spacers 138 and 140 that mechanically and electrically couple the first substrate 124 to the second substrate 126. The first side of the first substrate and the first side of the second substrate are asymmetrically coupled by two or more spacers. The second substrate 126 includes two dies 142 and 144 coupled to a first side of the second substrate 126. Two clips 146 and 148 are coupled to the two dies 142 and 144. Asymmetrically coupling the first substrate to the second substrate through the spacers may reduce stress on the clip and the die of the semiconductor package. The use of a leadframe and the use of spacers allows for structures in which the substrate and the die are not coupled in a stacked configuration.
The method of manufacturing a semiconductor package may further include encapsulating the lead frame on the first side and the second side. In various embodiments, the package may be encapsulated by transfer molding using an epoxy molding compound or by a liquid process using a liquid encapsulant. In various embodiments, the molding compound may include an epoxy, resin, or other encapsulating material. The second side of each of the first and second substrates 106 is exposed after encapsulation 150, as shown in fig. 21. The structure of the semiconductor package 120 may also provide better molding flow during the molding process. The method may further include trimming and forming the leads 152 of the semiconductor package 120 to orient them in a desired direction or directions, as shown in fig. 22. In various embodiments, the method may further include coupling a heat spreader to the second side of the first substrate, the second side of the second substrate, the second side of the first die, the second side of the second die, or any combination thereof.
Embodiments of the method of forming a semiconductor package may include wherein the first panel of the first substrate and the second panel of the second substrate each comprise one of a direct bonded copper substrate (DBC), an Insulated Metal Substrate Technology (IMST) substrate, an Active Metal Bonded (AMB) substrate, or any combination thereof.
Embodiments of methods of forming a semiconductor package may include wherein the two or more spacers may include a conductive material and electrically couple the first substrate to the second substrate.
Embodiments of methods of forming semiconductor packages may include wherein the first conductive material and the second conductive material comprise one of a solder paste or a sinter paste.
Embodiments of the semiconductor package may include wherein the two or more dies include an Insulated Gate Bipolar Transistor (IGBT) and a Fast Recovery Die (FRD).
Embodiments of the semiconductor package may include wherein the first substrate and the second substrate comprise a direct bond copper substrate having a doping with zirconium dioxide (ZrO)2) Alumina (Al)2O3) One of a ceramic, a silicon nitride (Si3N4) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof.
Embodiments of the semiconductor package may include wherein the two or more spacers may include a conductive material and electrically couple the first substrate to the second substrate.
Where specific embodiments of semiconductor packages and implementations of components, sub-components, methods and sub-methods are mentioned in the above description, it should be apparent that various modifications can be made without departing from the spirit thereof, and that the embodiments, implementations of components, sub-components, methods and sub-methods can be applied to other semiconductor packages.

Claims (10)

1. A semiconductor package, comprising:
a first substrate comprising two or more dies coupled to a first side of the first substrate, wherein a clip is coupled to each of the two or more dies;
a second substrate comprising two or more dies coupled to a first side of the second substrate, wherein a clip is coupled to each of the two or more dies;
two or more spacers coupled to the first side of the first substrate; and
a lead frame included between the first substrate and the second substrate;
a molding compound encapsulating said lead frame, wherein
A second side of each of the first substrate and the second substrate is exposed through the molding compound; and is
Wherein a perimeter of the first substrate and a perimeter of the second substrate do not completely overlap when coupled by the two or more spacers.
2. The semiconductor package of claim 1, further comprising a heat spreader coupled with one of the second side of the first substrate, the second side of the second substrate, or any combination thereof.
3. The semiconductor package of claim 1, wherein the two or more spacers are comprised of a conductive material and electrically couple the first substrate to the second substrate.
4. A semiconductor package, comprising:
a lead frame;
a first substrate mechanically and electrically coupled to a first side of the leadframe, the first substrate comprising two or more dies on a first side of the first substrate, wherein a clip is coupled to each die of the two or more dies;
a second substrate mechanically and electrically coupled to the second side of the leadframe, the second substrate comprising two or more dies on the first side of the second substrate, wherein a clip is coupled to each die of the two or more dies;
two or more spacers coupled to the first side of each of the first and second substrates; and
a molding compound encapsulating the first and second sides of the leadframe;
wherein the first side of the first substrate and a first side of the second substrate are asymmetrically coupled by the two or more spacers.
5. The semiconductor package of claim 4, further comprising a heat spreader coupled with one of the second side of the first substrate, the second side of the second substrate, or any combination thereof.
6. A method of forming a semiconductor package, the method comprising:
providing a first panel of a first substrate and a second panel of a second substrate;
printing a first conductive bonding material on a first side of the first panel of substrates and a second side of the first panel of first substrates in predetermined locations;
coupling two or more dies to each substrate of the first panel of first substrates and to each substrate of the second panel of second substrates at the predetermined locations;
dispensing a second conductive material onto a second side of each of the two or more dies;
coupling a clip to each of the two or more dies;
electrically coupling the two or more dies to each substrate of the first panel of first substrates and to each substrate of the second panel of second substrates;
cutting each of the first and second panels into a plurality of first and second substrates, respectively;
dispensing solder onto a plurality of predetermined locations on the first side of each of the plurality of first substrates and each of the plurality of second substrates;
coupling a first substrate of the plurality of first substrates to a first side of a lead frame;
coupling two or more spacers to a first side of the first substrate; and
coupling a first side of a second substrate of the plurality of second substrates to the two or more spacers and to a second side of the leadframe.
7. The method of claim 6, further comprising: trimming the lead frame to expose a plurality of leads and form the leads.
8. The method of claim 6, further comprising: encapsulating the lead frame on the first side and the second side, wherein the second side of each of the plurality of first substrates and the plurality of second substrates is exposed.
9. The method of claim 6, further comprising: coupling a heat spreader with one of the second side of the first substrate of the plurality of first substrates, the second side of the second substrate of the plurality of second substrates, or any combination thereof.
10. The method of claim 6, wherein the first side of the first substrate and a first side of the second substrate are asymmetrically coupled by the two or more spacers.
CN202010758504.5A 2019-08-02 2020-07-31 Low stress asymmetric two-sided module Pending CN112310016A (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201962882119P 2019-08-02 2019-08-02
US62/882,119 2019-08-02
US16/678,039 US11462515B2 (en) 2019-08-02 2019-11-08 Low stress asymmetric dual side module
US16/678,039 2019-11-08
US16/733,322 2020-01-03
US16/733,322 US11469163B2 (en) 2019-08-02 2020-01-03 Low stress asymmetric dual side module

Publications (1)

Publication Number Publication Date
CN112310016A true CN112310016A (en) 2021-02-02

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Country Status (1)

Country Link
CN (1) CN112310016A (en)

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