JPH0511337B2 - - Google Patents

Info

Publication number
JPH0511337B2
JPH0511337B2 JP62087133A JP8713387A JPH0511337B2 JP H0511337 B2 JPH0511337 B2 JP H0511337B2 JP 62087133 A JP62087133 A JP 62087133A JP 8713387 A JP8713387 A JP 8713387A JP H0511337 B2 JPH0511337 B2 JP H0511337B2
Authority
JP
Japan
Prior art keywords
data
directory
memory
shared memory
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62087133A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63253448A (ja
Inventor
Soichi Takatani
Yoshihiro Myazaki
Hiroaki Fukumaru
Yoshiaki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62087133A priority Critical patent/JPS63253448A/ja
Publication of JPS63253448A publication Critical patent/JPS63253448A/ja
Publication of JPH0511337B2 publication Critical patent/JPH0511337B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP62087133A 1987-04-10 1987-04-10 マルチ計算機装置 Granted JPS63253448A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62087133A JPS63253448A (ja) 1987-04-10 1987-04-10 マルチ計算機装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62087133A JPS63253448A (ja) 1987-04-10 1987-04-10 マルチ計算機装置

Publications (2)

Publication Number Publication Date
JPS63253448A JPS63253448A (ja) 1988-10-20
JPH0511337B2 true JPH0511337B2 (fr) 1993-02-15

Family

ID=13906464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62087133A Granted JPS63253448A (ja) 1987-04-10 1987-04-10 マルチ計算機装置

Country Status (1)

Country Link
JP (1) JPS63253448A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2595753B2 (ja) * 1990-03-30 1997-04-02 日本電気株式会社 キャッシュメモリの無効化方式
JP3228182B2 (ja) 1997-05-29 2001-11-12 株式会社日立製作所 記憶システム及び記憶システムへのアクセス方法
JP2001167040A (ja) 1999-12-14 2001-06-22 Hitachi Ltd 記憶サブシステム及び記憶制御装置
US6684209B1 (en) 2000-01-14 2004-01-27 Hitachi, Ltd. Security method and system for storage subsystem
JP4651230B2 (ja) 2001-07-13 2011-03-16 株式会社日立製作所 記憶システム及び論理ユニットへのアクセス制御方法
JP4719957B2 (ja) 2000-05-24 2011-07-06 株式会社日立製作所 記憶制御装置及び記憶システム並びに記憶システムのセキュリティ設定方法
KR100515059B1 (ko) * 2003-07-22 2005-09-14 삼성전자주식회사 멀티프로세서 시스템 및 멀티프로세서 시스템의 캐쉬일관성 유지 방법
CN102609362A (zh) * 2012-01-30 2012-07-25 复旦大学 一种共享高速缓存动态划分方法与电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172582A (en) * 1981-04-15 1982-10-23 Hitachi Ltd Cash memory control method
JPS60134948A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd デ−タ処理装置
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
JPS62115553A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd バッファストレイジ無効化処理方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172582A (en) * 1981-04-15 1982-10-23 Hitachi Ltd Cash memory control method
JPS60134948A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd デ−タ処理装置
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
JPS62115553A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd バッファストレイジ無効化処理方式

Also Published As

Publication number Publication date
JPS63253448A (ja) 1988-10-20

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