JPH05110541A - Pattern detecting circuit - Google Patents

Abstract

PURPOSE:To realize the pattern detecting circuit of a small scale for detecting a pattern in input data at a high speed, with regard to the circuit for detecting a fact that the data inputted by an N bit unit continues the same pattern by a prescribed number of times, in a device for executing a processing by an N bit unit. CONSTITUTION:The circuit is constituted by providing a data converting means 10 for converting serial input data of N bits to N pieces of parallel data, a pattern non-coincidence detecting means 20 for comparing the present pattern P1 outputted from the data converting means 10, and patterns P2-Pn of a first prescribed number of stages, detecting a non-coincidence and outputting it, and a continuous coincidence detecting means 30 for detecting a fact that an output of the pattern non-coincidence detecting means 20 is not outputted continuously by a second prescribed number of stages (m).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for processing in units of N bits, in which data input in units of N bits is
The present invention relates to a circuit that detects that the same pattern has been repeated a predetermined number of times.

For example, in a digital synchronous terminal device, etc., an increasing number of devices perform processing in units of bytes (8 bits) in order to improve the processing efficiency in the device. Therefore, it is becoming more and more important to give meaning to a byte-unit pattern inside the device, and it is necessary to accurately detect the pattern.

There is a demand for a small-scale circuit capable of detecting a pattern at high speed.

[0004]

2. Description of the Related Art FIG. 5 shows a diagram for explaining a conventional example.
(A) shows a configuration of a conventional example, 11 in the figure is a data extraction circuit for extracting a pattern written in a designated byte of input data, and 20A is a processing device for processing the extracted pattern. (Hereinafter referred to as CPU), 30A
Is a random access memory (hereinafter referred to as RAM) for writing the extracted pattern.

(B) is a diagram for explaining the contents of the RAM 30A. Here, this is an example in which a pattern in units of pits has meaning, and for example, 0, 1, 0, 1, 0, 1, 0,
The pattern is detected when 1 is repeated 12 times, and has a region for writing data in 12 stages.

Therefore, the 8-bit pattern extracted by the data extraction circuit 11 is written in the RAM 30A, and the next 8 bits are written.
When a bit pattern is input, the previously input pattern is moved down by one step, and the currently input pattern is written in the uppermost step.

In this way, the CPU 2 is stored in the RAM 30A.
The latest 8-bit 12-stage data is always written under the control of 0A. Each time a new pattern is written, the CPU 20A compares data of 12 stages for each bit, and when all the bits match 12 stages, the pattern is detected and the pattern is output.

[0008]

In the above-mentioned conventional example, the extraction of patterns is performed by hardware, and the continuity of patterns and the type of patterns are detected by software.

In recent years, communication devices have been increasing in data rate, and more and more are being controlled by software. Therefore, the CPU 20A in the communication device
There is a problem that the processing load of the software increases and the processing speed of software cannot keep up with the processing speed required by the device.

Therefore, the CPU 20 for controlling the entire apparatus
It is necessary to reduce the load on the software of A as much as possible, and it is required to perform pattern detection by hardware.

The present invention seeks to realize a small-scale pattern detection circuit for detecting a pattern in input data at high speed.

[0012]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 10 is a data conversion means for converting N-bit serial input data into N parallel data, and 20 is a current pattern P1 output from the data conversion means 10 and a pattern P2 having a first predetermined number of stages. Is a pattern mismatch detection means for comparing and comparing Pn to Pn and outputting the detected mismatch, and 30 detects that the output of the pattern mismatch detection means 20 is not continuously output for a second predetermined number of stages, m stages. It is a continuous coincidence detecting means.

Further, the continuous coincidence detecting means 30 includes a shift register 32 having a second predetermined number of stages m and a shift register 32.
NOR circuit 320 for taking the NOR of the output of each stage of
It consists of.

[0014]

Function: The serial input data is converted into N parallel data. This data is input to the pattern mismatch detection means 20 to detect mismatch of the first predetermined number of stages and n stages, and N
If even one of the data in the book has a mismatch, a mismatch detection signal is output.

This mismatch detection signal is a continuous match detection circuit 3
0, the continuous match detection circuit 30 detects that the second predetermined number of stages m is not continuously output, and outputs (n + m−
1) It is possible to configure a circuit on a small scale that can detect the continuation of the same pattern of stages at high speed.

[0016]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
The present embodiment is an example in which N = 8, n = 3, and m = 10, and detects that the same pattern continues for 12 frames.

Reference numeral 11 in the figure is a data extraction circuit for extracting a designated byte in the input data, and 12 is a conversion unit for converting 8-bit serial data into eight parallel data inputs 1 →
8 data conversion circuit, 21 outputs 3 high-level mismatch (hereinafter referred to as “H”) when detecting mismatches in 3 consecutive frames, 31 outputs 3 continuous mismatch detection circuit 21 Is a 10 consecutive coincidence detection circuit that outputs "H" when it is detected that the "low" level (hereinafter referred to as "L") is consecutive 10 times.

FIG. 3 shows a time chart of the embodiment of the present invention. The operation of FIG. 2 will be described with reference to a time chart.
The circled numbers in FIG. 2 use the same numbers as in the time chart of FIG.

It is data in byte units extracted by the data extraction circuit. It is shown that a of'is composed of 8 bits of a1, a2, ..., A8. The same applies to b and c.

8 of a1 to a8 input in serial
The output obtained by converting the bit data into eight parallel data by the 1 → 8 data conversion circuit 12 is shown. -1 to 3 are data in the three consecutive mismatch detection circuits 21, -1 is data of the current frame, -2 is data of one frame before, and -3 is data of two frames before.

-1 to 3 are compared, and if there is even one mismatch data, "H" is output from the three consecutive mismatch detection circuits 21. -1 to 10 are data in the 10 consecutive match detection circuit 31, which are outputs obtained by shifting the output of the 3 consecutive mismatch detection circuit 21 by 10 stages for each frame.

-1 to 10 are compared, and if there is even one "H", the 10 consecutive match detection circuit 31 outputs "L". This pattern is output when the 10 consecutive match detection circuit 31 detects 10 consecutive match. When 10 consecutive matches cannot be detected, the pattern in which the 10 consecutive matches are finally detected is output.

FIG. 4 is a diagram for explaining a ten consecutive match detection circuit according to the embodiment of the present invention. Numerals 301 to 310 are flip-flop circuits (hereinafter referred to as FF circuits) configuring the shift register 32, and 320 is a 10-input NOR circuit (hereinafter referred to as NOR circuit).

In the operation of this circuit, the outputs of the three consecutive mismatch detection circuits 21 are sequentially shifted by the FF circuits 301 to 310,
By inputting each output to the NOR circuit 320, “H” is output when 10 consecutive matches are detected.
With such a configuration, the pattern detection circuit can be configured on a small scale.

[0025]

According to the present invention, it is possible to realize, with a small scale, a circuit for extracting data at a designated position in input data and performing pattern detection at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a diagram for explaining a ten consecutive match detection circuit according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a conventional example.

[Explanation of symbols]

 10 data conversion means 11 data extraction circuit 12 1 → 8 data conversion circuit 20 pattern mismatch detection means 21 3 continuous mismatch detection circuit 20A CPU 30 continuous match detection means 31 10 continuous match detection circuit 32 shift register 30A RAM 301 to 310 FF circuit 320 NOR circuit

Claims (2)

[Claims] 1. A circuit for detecting that the data inputted in N-bit units continue the same pattern a predetermined number of times, and data conversion means for converting N-bit serial input data into N parallel data. (10), the current pattern (P1) output by the data conversion means (10), and the first predetermined number of patterns (P2 to P).
n), the pattern mismatch detection means (20) for detecting and outputting the mismatch, and the output of the pattern mismatch detection means (20) are not continuously output for the second predetermined stage number (m). A pattern detection circuit comprising a continuous coincidence detection means (30) for detecting 2. The continuous coincidence detection means (30) is a second predetermined number of stages (m) of shift registers (32) and a NOR circuit (N) for taking the NOR of each stage of the shift register (32). 320), the pattern detection circuit according to claim 1.