JP2003069392A - Pattern generating apparatus and communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern generating apparatus that can keep continuity of a pattern before and after a particular pattern even in the case of generating the pattern resulting from inserting the particular pattern with an optional length to part of a consecutive pattern. SOLUTION: A PN pattern generating section 12 generates a consecutive PN pattern P1 sequentially from a predetermined initial value, and a particular pattern generating section 12 generates the particular pattern P2 to be inserted to the PN pattern P1. A pattern traveling section 20 generates a pattern P5 advancing the PN pattern P1 by a prescribed time, a PN pattern selection section 22 selects the initial value of the PN pattern generating section 12 so that a pattern consecutive to the PN pattern finished just before the particular pattern P2 is inserted to the PN pattern P1 is placed just after the end of the particular pattern P2 on the basis of the pattern P5 advanced by the pattern traveling section 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generating device for generating a pseudo random pattern (hereinafter referred to as a PN pattern) and a communication device using the PN pattern generated by the pattern generating device. The present invention relates to a communication device capable of performing the above test.

[0002]

2. Description of the Related Art PN patterns are frequently used to test whether various devices are working properly. For example, in a semiconductor integrated circuit test apparatus (so-called IC tester), after writing a PN pattern to a semiconductor device as a test target, data is read from the semiconductor device and whether the read data matches an expected value or not. By determining, the semiconductor device is tested whether it is normally manufactured or not.

In a communication device such as an SDH (Synchronous Digital Hierarchy) multiplexer, information is divided into SDH frame units and transmitted. For example, SD in which a PN pattern is added to SOH (section overhead) is used.
The H-frame is transmitted and received between the communication devices, and the PN pattern received by the communication devices is investigated to perform a test on the communication of the communication devices.

Devices such as the semiconductor integrated circuit test device and the communication device are provided with a pattern generator for generating a PN pattern. This type of pattern generator includes a PN pattern generator that generates a parallel PN pattern, and a P
A parallel / serial conversion unit for converting the parallel PN pattern generated by the N pattern generation unit into serial is provided. Here, if the bit width of the PN pattern generator is N
Assuming that (N is an integer of 2 or more) bits, the N-bit PN pattern is output from the PN pattern generation unit every time the reference clock that defines the operation of the PN pattern generation unit is input.

The N-bit PN pattern output from the PN pattern generator is converted into a serial pattern in the parallel / serial converter, for example, in the order of the most significant bit (MSB) to the least significant bit (LSB). The above operation is repeated, and the parallel PN pattern output from the PN pattern generating unit is converted into a continuous serial PN pattern for each reference clock and output.

[0006]

By the way, among the above-mentioned various devices, particularly in a communication device for transmitting and receiving SDH frames, it is necessary to insert another pattern into a part of the PN pattern when adding the PN pattern to SOH. There is. Figure 7
FIG. 8 is a diagram showing how another pattern is inserted in a part of the PN pattern. Note that FIG. 7 illustrates a parallel PNPN pattern when the bit width of the PN pattern output from the above-described PN pattern generation unit is 10 bits. Further, in FIG. 7, in order to facilitate understanding, the PN pattern output from the PN pattern generating unit is shown by capital letters “A” to “Z”, and from the PN pattern generating unit, “A” to “A”. It is assumed that a pattern that is continuously repeated in the order of'Z 'is output. still,
The possible values of each of the alphabets "A" to "Z" are "0" or "1".

As shown in FIG. 7, the PN pattern P10,
Every time the reference clock CLK is input, P11 is output in synchronization with the reference clock CLK, and another pattern is inserted in a part thereof. Here, another pattern (hereinafter, referred to as a specific pattern) inserted in a part of the PN pattern output from the PN pattern generating unit is represented by a lower case alphabet, and its bit width is C. Since the specific pattern generator that generates the specific pattern also operates in synchronization with the above-described reference clock, the insertion position for the PN pattern is the time position at which the clock CLK is input (the rising edge of the clock CLK).

Now, consider the case where a specific pattern of bit width C is inserted into a PN pattern of bit width N. When the bit width C of the specific pattern is a natural number times the bit width N of the PN pattern (C = 2 in the example shown in FIG. 7A)
N) is time t12 to time t when the specific pattern is inserted.
In the period T10 between 14, the PN pattern generator generates P
If the generation of the N pattern is suspended and the generation of the PN pattern is restarted after the period T10, the continuity of the PN pattern before and after the period T10 in which the specific pattern is inserted is maintained. That is, in the example shown in FIG. 7A, the PN pattern of'J 'is output immediately before the period T10,
Immediately after the period T10, the PN pattern of'K 'is output.

However, the bit width C of the specific pattern
Is not a natural multiple of the bit width N of the PN pattern (C = 2N + 5 in the example shown in FIG. 7B, that is, 'a'-
In (25 bits of'y '), the continuity of the PN pattern before and after the period T11 in which the specific pattern is inserted cannot be maintained. That is, in the example shown in FIG. 7B, the period T11
Just before, the PN pattern of'J 'is output and the period T1
Immediately after 1, the PN pattern of'P 'is output.
Since the pattern generator provided in the conventional pattern generator operates in synchronization with the reference clock, the operation is restarted immediately after the period T11 shown in FIG. 7B to generate a PN pattern starting from'J '. I can't let you do it.

As described above, the conventional pattern generator is
When the bit width C of the inserted specific pattern is not a natural number multiple of the bit width N of the PN pattern (parallel) output from the pattern generation unit, the continuity of the PN pattern can be maintained before and after the inserted specific pattern. could not. In recent years, the bit width C of the specific pattern to be inserted into the PN pattern is arbitrarily changed by setting, so that it is necessary to maintain the continuity of the PN pattern before and after the specific pattern regardless of the bit width of the specific pattern. .

The present invention has been made in view of the above circumstances. Even when a pattern in which a specific pattern having an arbitrary length is inserted in a part of a pattern having continuity is generated, the pattern before and after the specific pattern is generated. It is an object of the present invention to provide a pattern generator capable of maintaining the continuity of patterns and a communication device including the pattern generator.

[0012]

In order to solve the above-mentioned problems, the pattern generating apparatus of the present invention has a first pattern (P1) which is continuous from the set initial value (P0, P6).
A first pattern generating section (12), a second pattern generating section (14) generating a second pattern (P2) to be inserted into the first pattern (P1), and the first pattern (P1). The pattern progression part (2
0) and the first pattern (P5) advanced by the pattern progression unit (20) to the second pattern (P5).
2) An initial value (P6) of the first pattern generation unit (12) so that a pattern continuous with the first pattern (P1) that has ended immediately before insertion is positioned immediately after the end of the second pattern (P2). A selection unit (22) for selecting the
It is characterized by comprising an adding section (16) for adding the second pattern (P2) to the first pattern (P1) generated from the pattern generating section (12). According to the present invention, after the pattern advancing unit obtains a pattern advanced by a predetermined time with respect to the continuous first pattern output from the first pattern generating unit, the process ends immediately before the insertion of the second pattern from this pattern. Since a pattern is selected so that the pattern following the first pattern is located immediately after the end of the second pattern, and this pattern is input to the first pattern generation unit as an initial value, a part of the pattern having continuity is selected. Even when a pattern in which a specific pattern having an arbitrary length is inserted is generated, the continuity of the pattern can be maintained before and after the specific pattern. Further, the pattern generating apparatus of the present invention has an initial value (P6) selected by the selecting unit (22) at a predetermined timing when the second pattern (P2) is inserted into the first pattern (P1). Is provided with a control unit (10) for setting an initial value of the first pattern generation unit (12). Further, in the pattern generating apparatus of the present invention, the first pattern generating section (12) generates the first pattern (P1) for each predetermined unit, and the pattern advancing section (20) causes the first pattern (P1) to be generated. The first pattern (P1) is advanced by the predetermined time by advancing P1) by the predetermined number of the predetermined units. Further, in the pattern generating apparatus of the present invention, the pattern output from the adding unit (16) is a parallel pattern, and the conversion unit (18) that converts the parallel pattern into a temporally continuous serial pattern. ) Is provided. Further, in the pattern generating apparatus of the present invention, the time required for the pattern advancing unit (20) to advance the first pattern (P1) is the length of time required for the selecting unit (22) to select the initial value. It is characterized by being set according to. Further, a pattern generating apparatus of the present invention is a communication apparatus that divides and transmits information in units of frames (f1, f2), and the pattern generated by any one of the above pattern generating apparatuses is the frame (f1, f2). It is characterized in that it is included in a part of f2) for transmission.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a pattern generating device and a communication device according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a pattern generator according to an embodiment of the present invention. As shown in FIG. 1, the pattern generating apparatus according to the present embodiment includes a control unit 10, a PN pattern generating unit 12 as a first pattern generating unit, a specific pattern generating unit 14 as a second pattern generating unit, and an adding unit. The pattern adding unit 16, the parallel / serial converting unit 18 as a converting unit, the pattern advancing unit 20, and the PN pattern selecting unit 22 as a selecting unit are included.

The PN pattern generator 12 operates, for example, in synchronization with a reference clock (not shown) having a frequency of 100 MHz, and generates a PN pattern P1 as a first pattern which is continuous in order from a set initial value. As shown in FIG. 1, the PN pattern generation unit 12 receives the initial pattern P0 and the selection pattern P6 from the PN pattern selection unit 22, and any one of them is output from the control unit 10 as a control signal CS1. It is set as an initial value based on CS2. The P output from the PN pattern generator 12
The N pattern P1 is a parallel signal having a plurality of bit widths N (predetermined unit).

The specific pattern generator 14 generates a specific pattern P2 as a second pattern to be inserted into the PN pattern P1 output from the PN pattern generator 12. Like the PN pattern generating section 12, the specific pattern generating section 14 also operates in synchronization with a reference clock (not shown). Further, the specific pattern generation unit 14 outputs the specific pattern P at the timing when the control signal CS3 is output from the control unit 10.
2 is output. The specific pattern P2 output from the specific pattern generator 14 is a parallel signal having a plurality of bit widths C.

When the specific pattern generating section 14 outputs the specific pattern P2, the pattern adding section 16 outputs P
PN pattern 12 output from N pattern generation unit 12
On the other hand, the specific pattern P2 is overwritten and output, and when the specific pattern P2 is not generated by the specific pattern generation unit 14, the PN pattern P1 output from the PN pattern generation unit 12 is output as it is. Since the PN pattern P1 and the specific pattern P2 are parallel signals, the pattern P3 output by the pattern adding unit 16 is also a parallel signal. The parallel / serial converter 18
The parallel pattern P3 output from the pattern adding unit 16 is converted into a temporally continuous serial pattern and output as a serial PN pattern P4.

The pattern advancing section 20 outputs a pattern P5 obtained by advancing the PN pattern P1 output from the PN pattern generating section 12 by a predetermined time. As mentioned above, P
Since the N pattern P1 is a pattern in which the same pattern is repeated with a certain period, the pattern progression unit 20 uses the periodicity of the PN pattern P1 to temporally compare with the PN pattern P1 output from the PN pattern generating unit 12. The advanced pattern P5 can be output. The time for the pattern progression unit 20 to advance the PN pattern P1 is
It is set according to the time required for the processing performed by the PN pattern selection unit 22. Specifically, the time required for processing in the PN pattern selection unit 22 is 3 of the reference clock.
In the case of the number of clocks, the pattern progression unit 20 outputs (3
+ 1 = 4) The PN pattern P1 is advanced by the number of clocks.

When the specific pattern P2 is inserted into the PN pattern P1 output from the PN pattern generating unit 12, the PN pattern selection unit 22 determines that a pattern continuous with the PN pattern P1 immediately before the specific pattern P2 is inserted. The pattern is selected from the patterns P5 output from the pattern advancing unit 20 so as to be located immediately after the insertion of the specific pattern P2. The PN pattern selection unit 22 includes the specific pattern generation unit 1 from the control unit 10.
Control signal CS indicating that 4 is outputting a specific pattern
4 is input and the control signal CS4 is input, the selected pattern is held.

The schematic configuration of the pattern generating apparatus according to the embodiment of the present invention has been described above. Next, the PN pattern generating section 12, the pattern advancing section 20, and the
The details of the PN pattern selection unit 22 will be described in order. FIG. 2 is a block diagram showing the configuration of the PN pattern generation unit 12. Note that, in FIG. 2, for easy understanding, a pattern generation device for inputting 7-bit initial value data and generating a 10-bit PN pattern is illustrated as an example.

The pattern generating section 12 shown in FIG. 2 includes a switching section 30 as an input section for the initial value data P0 and ten exclusive OR circuits (for each of the PN pattern output lines L5). (Hereinafter referred to as EXOR circuit) 31 and the PN connected to the output terminal of this EXOR circuit 31
And a switching unit 32 connected to the pattern output line L5. The control signal CS1 and the reference clock CLK output from the control unit 10 in FIG. 1 are input to the switching unit 30, and seven bit registers B0 to B6 are provided inside thereof. A signal line L1 and a signal line L4 connected to a 7-bit output line L5 on the LSB side are connected to the bit registers B0 to B6, respectively. A signal line L3 is connected to the output side of each bit register B0 to B6, and the connection relationship between this signal line L3 and the ten EXOR circuits 31 is set according to the PN pattern to be generated.

Based on the control signal CS1 output from the control unit 10, the switching unit 30 fetches the initial pattern P0 input via the signal line L1 into each bit register B0 to B6 when generating the PN pattern. After the initial pattern P0 has been fetched once, the input is switched so that the signal inputted via the signal line L4 is fetched in each of the bit registers B0 to B6.

Further, the switching unit 32 has 10 bit registers therein. EXO for each bit register
The output terminal of the R circuit 31 and the signal line L2 are connected to each other. An output line L5 is connected to each bit register. The switching unit 32 takes in and outputs the signals output from the EXOR circuits 31 based on the control signal CS3 output from the control unit 10, or selects the selection pattern P6 input via the signal line L2. To switch between capturing and outputting.

Next, the connection relationship between the signal line L3 and the EXOR circuit 31 will be described in detail. Signal line L3 and EXO
The connection relationship with the R circuit 31 is PN shown in the following equation (1).
It is set based on the generator polynomial of the pattern. The operator "+" in the following formula is an exclusive OR. ^{f (x) = x 7 +} x + 1 ...... (1) x 0 = 1~x 6 shows the values that are respectively stored in the bit register B0~B6, x ⁷ ~x ¹⁶ bit output lines L5 The values appearing from B7 to bit B16 are shown.

When f (x) = 0 in the above equation (1), the following equation (2) is obtained. ^{x 7 = x + 1 x 8} = x 7 · x = x 2 + x x 9 = x 7 · x 2 = x 3 + x 2 x 10 = x 7 · x 3 = x 4 + x 3 x 11 = x 7 · x 4 = x ⁵ + x ⁴ x ¹² = x ⁶ + x ⁵ x ¹³ = x ⁶ + x + 1 x ¹⁴ = x ² +1 x ¹⁵ = x ³ + x x ¹⁶ = x ⁴ + x ² (2)

To obtain the connection relationship between the signal line L3 and the EXOR circuit 31 from the above equation (2), for example, the value x ⁸ appearing on the output line of the bit B8 is the value x ² stored in the bit register B2. Is an exclusive OR of the value x stored in the bit register B1 and the input end of the EXOR circuit 31 connected to the output line of the bit B8 and the bit register B2 and the bit register B1. Connect with the connecting line.

Next, the structure of the pattern progression unit 20 will be described. FIG. 3 is a block diagram showing the configuration of the pattern progression unit 20. Note that, in FIG. 3, in order to facilitate understanding, only the lower 7 bits of the 10-bit PN pattern P1 generated from the PN pattern generation unit 12 are input, and the PN pattern for 4 clocks of the reference clock CLK is input. The pattern advancing part which obtains the pattern P5 which advanced P1 is shown.

The PN pattern generator 12 shown in FIG.
The 10-bit PN pattern P1 is generated from the 7-bit initial pattern. The pattern progression unit 20 shown in FIG.
Uses a 7-bit PN pattern output from the PN pattern generator 12 at a certain point as an initial value,
By utilizing the periodicity of the N pattern P1, a pattern P5 that is ahead of the PN pattern P1 output from the PN pattern generating unit 12 by four clocks is output (generated).

The pattern progression unit 20 shown in FIG. 3 is provided with ten EXOR circuits 40 whose output ends are connected to the respective output lines L11 of the pattern P5. EXOR circuit 4
The input terminal of 0 is connected to at least three of the seven signal lines L10 to which the lower 7 bits of the PN pattern output from the PN pattern generation unit 12 are input. Signal line L1
0 and the EXOR circuit 40 are connected by a PN pattern P
It is set according to the time (the number of clocks) in which 1 is advanced.

Next, the connection relationship between the signal line L10 and the EXOR circuit 40 will be described. Now, as shown in FIG. 3, each of the signal lines L10 is set to bits b0 to b6, and each of the output lines L11 is set to bits b37 to b46. Here, the value of the pattern input to each bit b0 to b6 of the signal line L10 is x ⁰ = 1 to x ^6, and the value of the pattern appearing at each bit b37 to b46 of the output line L11 is x ³⁷ to x ⁴⁶ . To do. At this time, in order that the pattern P5 output from the output line L11 is advanced by 4 clocks with respect to the pattern input to the signal line L10, it is necessary to satisfy the following expression (3). The operator "+" shown in the following expression (3) is also an exclusive OR.

X ³⁷ = x ⁶ + x ³ + x ² + x + 1 x ³⁸ = x ⁴ + x ³ + x ² +1 x ³⁹ = x ⁵ + x ⁴ + x ³ + x x ⁴⁰ = x ⁶ + x ⁵ + x ⁴ + x ² x ⁴¹ = x ⁶ + x ⁵ + x ³ + x ¹ +1 x ⁴² = x ⁶ + x ⁴ + x ² +1 x ⁴³ = x ⁵ + x ³ +1 x ⁴⁴ = x ⁶ + x ⁴ + x x ⁴⁵ = x ⁵ + x ² + x + 1 x ⁴⁶ = x ⁶ + x ³ + x ² + x …… (3)

From the equation (3), the signal line L10 and EXOR
To obtain the connection relationship with the circuit 40, for example, the bit b3
The value x ³⁷ appearing on the output line of 7 is the pattern value 1 appearing in the bit b0, the pattern value x appearing in the bit b1, the pattern value x ² appearing in the bit b2, the pattern value x ³ appearing in the bit b3, and Since it is the exclusive OR of the pattern value x ⁶ appearing in the bit b6, the input end of the EXOR circuit 40 connected to the output line of the bit b37 and the bits b0, b1, b2, b3, b6 of the signal line L10. Connect with the signal line of.

The example of the configuration in which the pattern advancing unit 20 advances the PN pattern P1 by four clocks of the reference clock CLK has been described above. However, a plurality of circuits having different numbers of advancing clocks are provided and a circuit to be used is appropriately selected. It may be configured.

Next, details of the PN pattern selection unit 22 will be described. As described above, the PN pattern selection unit 22
When the specific pattern P2 is inserted into the PN pattern P1 output from the PN pattern generating unit 12, a pattern continuous with the PN pattern P1 immediately before the specific pattern P2 is inserted is immediately after the specific pattern P2 is inserted. Pattern P5 output from the pattern advancing unit 20 so that the selected pattern P6 is selected.
Is given to the PN pattern generator 12.

Now, in FIG. 7B, immediately after the inserted specific pattern (immediately after the period T11), 'K' is entered.
In order to obtain a PN pattern starting from (a pattern continuous with the PN pattern'J 'immediately before the insertion of the specific pattern), a pattern in which'K' is located at the 6th bit in the period from time t24 to time t25 Just get In other words, at time t24, the pattern'K '
If the PN pattern starting from the pattern "F" 5 bits before is obtained, the pattern "K" can be located at the 6th bit.

FIG. 4 is a diagram for qualitatively explaining the processing performed by the PN pattern selection unit 22. In the example shown in FIG. 4, the pattern P5 output from the pattern progression unit 20.
Pattern P for two clocks of the reference clock CLK in
Reference clock CL from 10, P11 (20 bits in total)
A pattern P6 (10 bits) for one clock of K is obtained.

In the example shown in FIG. 4, in order to position the pattern'K 'at the 6th bit, patterns P10 and P11 are placed.
Then, the data width is gradually narrowed down, and a total of 5 times of processing (processing for 5 clocks of the reference clock CLK) is performed to obtain the pattern P6 from the patterns P10 and P11. Here, as shown in FIG. 4, since the actual patterns P10 and P11 are provided with a plurality of narrowing down processes several hundreds of bits, if the narrowing down is performed at once, the narrowing down condition becomes complicated and the reference clock This is because the processing cannot be completed in time for one clock of CLK. In FIG. 4, the case where the pattern selection is performed for 5 clocks of the reference clock CLK is described as an example, but the PN pattern selection unit 22 shown in FIG. 1 uses the 3 clocks of the reference clock. It can be done in minutes.

Next, the operation of the pattern generator having the above-described structure according to the embodiment of the present invention will be described. FIG. 5 is a timing chart for explaining the operation of the pattern generator according to the embodiment of the present invention. When the pattern generator starts operating, the control unit 10 shown in FIG. 1 first outputs the control signal CS1 to the PN pattern generator 12. When this control signal CS1 is input, the switching unit 30 in the PN pattern generation unit 12 shown in FIG. 2 switches the input of each bit register B0 to B6 to the signal line L1 so that the initial pattern P0 is set to each bit register. B0
It is taken into B6. When the initial pattern P0 is taken into the bit registers B0 to B6, the control unit 10 outputs the control signal CS1 and switches the input of the bit registers B0 to B6 to the signal line L4. When the above operation is completed and the reference clock CLK is input, the 10-bit parallel PN pattern P1 is output from the output line L5.

When the control signal CS3 is not input from the control unit 10, the PN pattern P1 is input to the parallel / serial conversion unit 18 as the pattern P3 via the pattern addition unit 16 and output as the parallel PN pattern P4. It Further, the PN pattern P1 output from the PN pattern generating unit 12 is input to the pattern advancing unit 20, is converted into a pattern P5 which is advanced by 4 clocks with respect to the PN pattern P1, and is output. Referring to FIG. 5, for example, a pattern between time t1 and time t2 of pattern P5 (a pattern starting with'K 'and ending with'T')
Is the time t5 when the specific pattern P2 is not inserted.
It is the same pattern as the pattern P3 output from the pattern addition unit 16 between time t6. Note that, in FIG. 5, the pattern P3 between time t5 and time t6 is a pattern output from the pattern adding unit 16 when the specific pattern is overwritten.

The period from time t5 to time t6 is from time t1 to time t1.
It advances by 4 clocks with respect to the period of time t2. Therefore, the pattern that appears between time t1 and time t2 of pattern P5 (the same pattern that appears between time t5 and time t6 of pattern P3) is different from the pattern that appears between time t1 and time t2 of pattern P3. Four clocks ahead.

The pattern P5 output from the pattern advancing unit 20 is input to the PN pattern selecting unit 22 and the processing described with reference to FIG. It is selected and output as a selection pattern P6. For example, referring to FIG. 5, the pattern P5 has two patterns, that is, the pattern from time t1 to time t2 and the pattern in the cycle one clock before.
From the clock pattern, a continuous selection pattern P6 starting from the pattern'F 'from time t4 to time t5
Is generated. The selection pattern P6 is output to the PN pattern generation unit 12, but since the control signal CS2 is not output from the control unit 10 to the PN pattern generation unit 12 between time t4 and time t5, its value is PN
It is not taken into the bit register in the switching unit 32 provided in the pattern generating unit 12.

However, when the specific pattern P2 is added to the PN pattern P1 output from the PN pattern generating unit 12, the control signal CS3 is output to the specific pattern generating unit 14 at time t5, and as shown in FIG. A specific pattern starting from a'and ending with'j 'is overwritten on the PN pattern P1 (the specific pattern starting with'a' and ending with'j 'is selected by the pattern adding unit 16 and output as the pattern P3). Further, at this time, the control unit 10 outputs the control signal CS4 indicating that the specific pattern P2 is output, to the PN pattern selection unit 22.
Output to. With this control signal CS4, the PN pattern selection unit 22 holds the selected pattern, and as shown in FIG. 5, the selected pattern P6 (the pattern ('F' between time t4 and time t5) held after time t5. Pattern that starts with "O" and ends with "O"))
Output every time K is input.

When the quotient obtained by dividing the number of remaining bits of the specific pattern overwriting the PN pattern P1 by the number of bits of the specific pattern P1 is "1" or more, the above operation is performed every time the reference clock CLK is input. Repeat. However, when the quotient obtained by dividing the number of remaining bits of the specific pattern to be overwritten on the PN pattern P1 by the number of bits of the specific pattern P1 becomes smaller than “0”, the control unit 10 controls the control signal CS.
2 is output to the PN pattern generation unit 12 (in the example shown in FIG. 5, the control signal CS2 is output at time t6).

When this control signal CS2 is output, PN
The switching unit 32 in the pattern generation unit 12 loads the selection pattern P6 output from the PN pattern selection unit 22 into each register and outputs the selection pattern P6 to the pattern addition unit 16. In the example shown in FIG. 5, at time t6, the selection pattern P6 output from the PN pattern selection unit 22 is a pattern starting with “F” and ending with “O”, and this pattern is output to the pattern adding unit 16. . Time t6
In the period from time t7 to the time t7, the pattern adding unit 16 first selects the remaining pattern of the specific pattern P2 (the pattern starting with'k 'and ending with'o'), and then 5 bits from the LSB side ('K'). ~ 'O') selection pattern P6 is selected and output.

In FIG. 5, the period denoted by the reference symbol T1 is a period in which the specific pattern is added, and referring to the period before and after this period T1, the PN pattern'J 'which is completed immediately before the insertion of the specific pattern P2 is continued. The pattern'K 'is located immediately after the end of the period T1. In this way, the continuity of the PN pattern can be maintained before and after the period in which the specific pattern P2 is added. The pattern P3 to which the specific pattern P2 is added is converted into a serial PN pattern by the parallel / serial conversion unit 18, and P
It is output as N pattern P4.

The pattern generating apparatus according to the embodiment of the present invention has been described above. Next, the communication apparatus according to the embodiment of the present invention will be described. The communication device according to the present embodiment has a configuration including the above-described pattern generation device, and transmits data by dividing the data between the communication devices in frame units. FIG. 6 is a diagram showing an example of a frame generated by the communication device according to the embodiment of the present invention. In FIG. 6A, f1 and f2 indicate two temporally consecutive frames, and as shown in the figure, each frame f1 and f2
2 has section overheads h1 and h2.

The symbols tr1 to tr in the frame f1
The symbol tr6 in the arrow and frame f2 indicated by 5
The arrow indicated by ~ tr10 indicates the transmission / reception order of data in the frame. That is, a part of the section overhead and a part of the data part in which the data to be transmitted / received are stored are paired, and a plurality of these pairs are collected to form one frame. In the time-sequential frames f1 and f2, when data transmission / reception is completed in the order of the arrow indicated by the symbol tr5 in the frame f1, the arrow indicated by the symbol tr6 in the frame f2. Transmission and reception of data is started in this order.

FIG. 6B shows positions SR1 and SR2 at which the specific patterns to be inserted in the frames f1 and f2 are inserted.
FIG. As shown in FIG. 6B, the insertion positions SR1 and SR2 of the specific pattern are set to the frames f1 and f2.
It is set to the start position of the middle data transmission / reception.
When testing the communication device, the frames f1 and f
The PN pattern is stored in a portion other than the positions SR1 and SR2 where the specific pattern is arranged in the second pattern.

Here, for example, the PN patterns PN1 and PN2 arranged at positions temporally continuous with the position SR2 where the specific pattern is arranged need to maintain continuity. In order to generate such a pattern, the communication device of the present embodiment includes a PN pattern generator that generates a PN pattern having continuity before and after the specific pattern to be inserted. The positions SR1 and SR2 where the specific patterns shown in FIG. 6 are arranged are examples, and the positions may be arbitrary positions of the frames f1 and f2.

[0049]

As described above, according to the present invention,
After the pattern advancing unit obtains a pattern advanced by a predetermined time with respect to the continuous first pattern output from the first pattern generating unit, the pattern is continued from this pattern to the first pattern finished immediately before the insertion of the second pattern. A pattern is selected so that the pattern is located immediately after the end of the second pattern, and this pattern is input to the first pattern generation unit as an initial value. Therefore, a part of the pattern having continuity has an arbitrary length. Even when a pattern in which the specific pattern is inserted is generated, there is an effect that the continuity of the pattern can be maintained before and after the specific pattern.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a pattern generation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a PN pattern generation unit 12.

3 is a block diagram showing a configuration of a pattern progression unit 20. FIG.

FIG. 4 is a diagram for qualitatively explaining the processing performed by the PN pattern selection unit 22.

FIG. 5 is a timing chart for explaining the operation of the pattern generation device according to the embodiment of the present invention.

FIG. 6 is a diagram showing an example of a frame generated by a communication device according to an embodiment of the present invention.

FIG. 7 is a diagram showing how another pattern is inserted in a part of a PN pattern.

[Description of Reference Signs] 10 control unit 12 PN pattern generation unit (first pattern generation unit) 14 specific pattern generation unit (second pattern generation unit) 16 pattern addition unit (addition unit) 18 parallel / serial conversion unit (conversion unit) 20 pattern progression unit 22 PN pattern selection unit (selection unit) f1, f2 frame P0 initial pattern (initial value) P1 PN pattern (first pattern) P2 specific pattern (second pattern) P5 pattern (advanced PN pattern) P6 Selection pattern (initial value)

Claims (6)

[Claims] 1. A first continuous number in order from a set initial value
A first pattern generating section for generating a pattern, a second pattern generating section for generating a second pattern to be inserted into the first pattern, a pattern advancing section for advancing the first pattern for a predetermined time, and the pattern advancing Initial value of the first pattern generation unit so that a pattern continuous from the first pattern finished immediately before the insertion of the second pattern from the first pattern advanced by the unit is located immediately after the end of the second pattern. A pattern generation device comprising: a selection unit for selecting the first pattern generation unit; and an addition unit configured to add the second pattern to the first pattern generated by the first pattern generation unit. 2. A control unit that sets the initial value selected by the selection unit to the initial value of the first pattern generation unit at a predetermined timing when the second pattern is inserted into the first pattern. The pattern generator according to claim 1, wherein 3. The first pattern generating unit generates the first pattern for each predetermined unit, and the pattern advancing unit advances the first pattern by a predetermined unit number of the predetermined unit. The pattern generation device according to claim 1 or 2, wherein the first pattern is advanced by the predetermined time. 4. The pattern output from the adding unit is
The pattern generating apparatus according to claim 1, further comprising a conversion unit that is a parallel pattern and that converts the parallel pattern into a serial pattern that is temporally continuous. . 5. The method according to claim 1, wherein the time for which the pattern advancing unit advances the first pattern is determined according to the time required for the selecting unit to select the initial value. The pattern generator according to claim 1. 6. A communication device for transmitting information by dividing it into frame units, wherein the pattern generated by the pattern generating device according to claim 1 is part of the frame. A communication device characterized by being included in and transmitted.