JPH05110430A - Phase locked loop oscillation circuit - Google Patents

Phase locked loop oscillation circuit

Info

Publication number
JPH05110430A
JPH05110430A JP3130133A JP13013391A JPH05110430A JP H05110430 A JPH05110430 A JP H05110430A JP 3130133 A JP3130133 A JP 3130133A JP 13013391 A JP13013391 A JP 13013391A JP H05110430 A JPH05110430 A JP H05110430A
Authority
JP
Japan
Prior art keywords
phase
input signal
section
input
vco
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3130133A
Other languages
Japanese (ja)
Inventor
Tatsuyoshi Hamada
樹欣 浜田
Yoko Amagasa
陽子 天笠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP3130133A priority Critical patent/JPH05110430A/en
Publication of JPH05110430A publication Critical patent/JPH05110430A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To control an operating frequency F to be F=f0 by devising a circuit such that a control is not stopped due to synchronism going out of a limit of the operating frequency F=f0+ or -DELTAf different from a conventional PLO circuit and no alarm is raised in a system on the way even when an input signal is interrupted. CONSTITUTION:A detection voltage representing an internal phase and that for an input signal phase are detected by a phase comparator 10 and its detection voltage is fed to a low pass filter 20, the result is amplified by an operational amplifier 30 and its output voltage is fed to a VCO section 50. The output signal of the operational amplifier in the phase locked loop oscillator circuit feeding back the output of the VCO section to the phase comparator is inputted to a phase change detection section 1 to detect whether or not the phase of the input signal is largely fluctuated, and the result of detection is inputted to a phase change discrimination section 2 with an input interrupt signal. When the input signal is interrupted or the phase is largely fluctuated, the output voltage is fed to the VCO section 50 by setting 0V to an analog switch 3 and the operating frequency F is automatically converged to f0, and when the phase is not largely fluctuated even in the case of the interrupted input signal received, the output voltage is fed to the VCO section 50 as it is.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は位相同期発振回路(以下
PLO回路という)に関し、特に電圧制御発振器(VC
O)の周波数を正確に入力信号の平均周波数に一致させ
る自動周波数制御作用を改良したPLO回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillator (hereinafter referred to as PLO circuit), and more particularly to a voltage controlled oscillator (VC).
The present invention relates to a PLO circuit having an improved automatic frequency control function for accurately matching the frequency of O) with the average frequency of the input signal.

【0002】[0002]

【従来の技術】従来のPLO回路は図2に示すように、
位相比較器10で初期位相θi(図の201)とVCO
部50の出力であるループバックの位相θo(図の20
5)とを比較し、その位相差分|θi−θo|(図の2
02)が低域フィルタ20を経た後にOPアンプ30へ
の入力電圧Vi(図の203)となり、さらにOPアン
プ30の出力電圧Vo(図の204)が、大きく振られ
ていなければリレー40は動作せず、そのままVCO部
50へ渡される。出力電圧Voが大きく振られていたと
きは、リレー40が動作して出力電圧Vo=0Vとして
VCO部50へ渡され、動作周波数F=f0に自動収束
する。そして、VCO部50の出力の一部を再びVCO
部50の出力のループバックの位相θo(図の205)
として位相比較器10に戻し、再び初期位相θiと比較
する。この繰返しを行って自動周波数制御動作を行なっ
ていた。
2. Description of the Related Art A conventional PLO circuit, as shown in FIG.
In the phase comparator 10, the initial phase θi (201 in the figure) and VCO
The loopback phase θo (20 in the figure
5) and the phase difference | θi-θo |
02) becomes the input voltage Vi (203 in the figure) to the OP amplifier 30 after passing through the low-pass filter 20, and the output voltage Vo (204 in the figure) of the OP amplifier 30 is not largely shaken, the relay 40 operates. Instead, it is directly passed to the VCO unit 50. When the output voltage Vo is largely swung, the relay 40 operates and is passed to the VCO unit 50 as the output voltage Vo = 0V, and automatically converges to the operating frequency F = f0. Then, a part of the output of the VCO section 50
Loopback phase θo of the output of the unit 50 (205 in the figure)
Is returned to the phase comparator 10 and again compared with the initial phase θi. By repeating this, the automatic frequency control operation was performed.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のPLO
回路では、入力信号の位相が大きく変動した場合、動作
周波数F=f0に自動収束するEx−ORの位相比較回
路等で構成されていた。しかし、内部の基本信号周波数
に比べ位相比較周波数が極端に小さい場合に、ループゲ
インが相対的に小さくなったり、内部と入力の位相同期
点が所望のポイントにならなかったりする場合のループ
ゲインを保証するために、増幅器を入れてループゲイン
を上げていた。この結果入力信号の位相が大きく変動し
た時に正常な同期制御動作から外れOPアンプの最大オ
フセット値までVCOの制御電圧が振られ、この結果こ
のPLOの出力は、大きく基本周波数からずれる欠点が
ある。特に中継装置として構成されている場合には、前
後の周波数ずれが後段に多大な影響を与え、最悪後段の
故障に間違えられる場合が生じる。また、これらの制御
をリレーで行っているが、リレーは外部ショックで誤動
作することがあり接点不良をおこすという欠点があっ
た。
DISCLOSURE OF THE INVENTION The conventional PLO described above
The circuit is composed of an Ex-OR phase comparison circuit or the like that automatically converges to the operating frequency F = f0 when the phase of the input signal largely changes. However, when the phase comparison frequency is extremely small compared to the internal basic signal frequency, the loop gain becomes relatively small, or the loop gain when the internal and input phase synchronization points do not reach the desired points. In order to guarantee, the amplifier was put in and loop gain was raised. As a result, when the phase of the input signal largely fluctuates, the normal synchronous control operation deviates, and the control voltage of the VCO fluctuates up to the maximum offset value of the OP amplifier. As a result, the output of this PLO largely deviates from the fundamental frequency. In particular, in the case of being configured as a relay device, the frequency shift between the front and the rear has a great influence on the subsequent stage, and in the worst case, it may be mistaken for a failure in the subsequent stage. Further, although these controls are performed by a relay, there is a drawback that the relay may malfunction due to an external shock and cause a contact failure.

【0004】[0004]

【課題を解決するための手段】本発明の位相同期発振回
路は、内部位相と入力信号位相の検波電圧を位相比較器
で検出し、この検出電圧を低域フィルタを通過させた後
にOPアンプで増幅された出力電圧をVCO部に供給
し、このVCO部の出力を前記位相比較器に帰還する位
相同期発振回路において、前記OPアンプの出力信号を
位相変化検出部に入力し入力信号の位相が大きく変動し
たか否かの検出を行い、その検出結果を位相変化判定部
に入力断信号とともに入力し、入力信号断又は位相が大
きく変動していたならば前記出力電圧をアナログスイッ
チで0VとしてVCO部へ供給し、動作周波数F=f0
に自動収束させ、逆に入力信号断でも位相が大きく変動
していなければ前記出力電圧をそのまま前記VCO部へ
供給する。
A phase-locked oscillator circuit of the present invention detects a detection voltage of an internal phase and an input signal phase with a phase comparator, passes the detection voltage through a low pass filter, and then uses an OP amplifier. In the phase-locked oscillator circuit which supplies the amplified output voltage to the VCO unit and feeds back the output of the VCO unit to the phase comparator, the output signal of the OP amplifier is input to the phase change detection unit and the phase of the input signal is changed. It is detected whether or not there is a large change, and the detection result is input to the phase change determination unit together with the input disconnection signal. If the input signal is disconnected or the phase is greatly changed, the output voltage is set to 0 V by the analog switch and the VCO Supplied to the operating section and operating frequency F = f0
On the contrary, if the phase does not largely change even when the input signal is broken, the output voltage is directly supplied to the VCO section.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は、本発明の一実施例のブロック図である。本
実施例では従来の回路に位相変化検出部1、位相変化判
定部2、アナログスイッチ3を追加している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, a phase change detector 1, a phase change determiner 2, and an analog switch 3 are added to the conventional circuit.

【0006】次に本回路の動作を説明する。位相比較器
10で初期位相θi(図の101)とVCO部50の出
力であるループバックの位相θo(図の108)とを比
較し、その位相差分|θi−θo|(図の102)が低
域フィルタ20を経た後に、OPアンプ30への入力電
圧Vi(図の103)となる。ここでOPアンプ30へ
の入力電圧Vi(図の103)がΔvだけ変化していた
場合に、出力電圧Vo=0V±Δvoと変化する。
Next, the operation of this circuit will be described. The phase comparator 10 compares the initial phase θi (101 in the figure) and the loopback phase θo (108 in the figure) which is the output of the VCO unit 50, and the phase difference | θi−θo | (102 in the figure) is calculated. After passing through the low-pass filter 20, it becomes the input voltage Vi (103 in the figure) to the OP amplifier 30. Here, when the input voltage Vi (103 in the drawing) to the OP amplifier 30 changes by Δv, the output voltage changes as Vo = 0V ± Δvo.

【0007】この出力電圧Vo(図の104)を位相変
化検出部1に入力し、入力信号の位相が大きく変動した
か否かの検出を行う。その検出結果105を位相変化判
定部2に入力断信号106とともに入力する。入力断、
又は、位相が大きく変動していたならば判定結果107
がアナログスイッチ3を切替えて、出力電圧Vo=0V
としてVCO部50へ渡し動作周波数F=f0に自動収
束する。入力断でも、位相が大きく変動していなければ
判定結果107は、アナログスイッチ3を切替えずに出
力電圧Vo=0V±ΔvoをそのままVCO部50へ渡
す。
This output voltage Vo (104 in the figure) is input to the phase change detector 1 to detect whether or not the phase of the input signal has changed significantly. The detection result 105 is input to the phase change determination unit 2 together with the input disconnection signal 106. Input cut,
Alternatively, if the phase is largely changed, the determination result 107
Switches the analog switch 3 and the output voltage Vo = 0V
Is passed to the VCO unit 50 and automatically converges to the operating frequency F = f0. Even if the input is disconnected, if the phase is not largely changed, the determination result 107 passes the output voltage Vo = 0 V ± Δvo to the VCO unit 50 without changing the analog switch 3.

【0008】さらに、VCO部50の出力の一部をVC
O部50の出力のループバックの位相θo(図の10
8)として位相比較器10に戻し、再び初期位相θi
(図の101)と比較する。以上の繰返しで自動周波数
制御を行なう。
Further, a part of the output of the VCO section 50 is converted to VC.
Loopback phase θo of the output of the O unit 50 (10 in the figure
8) is returned to the phase comparator 10 and the initial phase θi is returned again.
(101 in the figure). Automatic frequency control is performed by repeating the above.

【0009】[0009]

【発明の効果】以上説明したように、本発明は従来のP
LO回路のように動作周波数F=f0±Δfの限界点で
振り切ってしまう場合だけでなく、入力信号断の時にも
ある途中のシステムで警報を上げることなくF=f0に
制御可能である。又、リレーの代わりにアナログスイッ
チを用いることで、機械的な欠点を取り除ける上に、あ
らかじめアナログスイッチにレベルを設定しておけば意
図的な周波数制御を行うことができる効果もある。
As described above, according to the present invention, the conventional P
It is possible to control to F = f0 without raising an alarm not only in the case of swinging off at the limit point of the operating frequency F = f0 ± Δf as in the case of the LO circuit but also in a system in the middle when the input signal is cut off. Further, by using an analog switch instead of the relay, there is an effect that a mechanical defect can be removed, and if a level is set in advance in the analog switch, intentional frequency control can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来のPLO回路のブロック図である。FIG. 2 is a block diagram of a conventional PLO circuit.

【符号の説明】[Explanation of symbols]

1 位相変化検出部 2 位相変化判定部 3 アナログスイッチ 10 位相比較器 20 低域フィルタ 30 OPアンプ 40 リレー 50 VCO部 1 Phase Change Detection Section 2 Phase Change Judgment Section 3 Analog Switch 10 Phase Comparator 20 Low-pass Filter 30 OP Amplifier 40 Relay 50 VCO Section

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内部位相と入力信号位相の検波電圧を位
相比較器で検出し、この検出電圧を低域フィルタを通過
させた後にOPアンプで増幅された出力電圧をVCO部
に供給し、このVCO部の出力を前記位相比較器に帰還
する位相同期発振回路において、前記OPアンプの出力
信号を位相変化検出部に入力し入力信号の位相が大きく
変動したか否かの検出を行い、その検出結果を位相変化
判定部に入力断信号とともに入力し、入力信号断又は位
相が大きく変動していたならば前記出力電圧をアナログ
スイッチで0VとしてVCO部へ供給し、動作周波数F
=f0に自動収束させ、逆に入力信号断でも位相が大き
く変動していなければ前記出力電圧をそのまま前記VC
O部へ供給することを特徴とする位相同期発振回路。
1. A detection voltage of an internal phase and an input signal phase is detected by a phase comparator, the detected voltage is passed through a low pass filter, and then an output voltage amplified by an OP amplifier is supplied to a VCO section. In a phase-locked oscillator circuit that feeds back the output of a VCO unit to the phase comparator, the output signal of the OP amplifier is input to a phase change detection unit to detect whether or not the phase of the input signal has significantly changed, and the detection is performed. The result is input to the phase change determination unit together with the input disconnection signal, and if the input signal is disconnected or the phase greatly fluctuates, the output voltage is supplied to the VCO unit as 0 V by the analog switch, and the operating frequency F
= F0, and if the phase does not fluctuate significantly even when the input signal is broken, the output voltage is directly changed to the VC
A phase-locked oscillating circuit characterized by supplying to the O section.
JP3130133A 1991-06-03 1991-06-03 Phase locked loop oscillation circuit Pending JPH05110430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3130133A JPH05110430A (en) 1991-06-03 1991-06-03 Phase locked loop oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3130133A JPH05110430A (en) 1991-06-03 1991-06-03 Phase locked loop oscillation circuit

Publications (1)

Publication Number Publication Date
JPH05110430A true JPH05110430A (en) 1993-04-30

Family

ID=15026745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3130133A Pending JPH05110430A (en) 1991-06-03 1991-06-03 Phase locked loop oscillation circuit

Country Status (1)

Country Link
JP (1) JPH05110430A (en)

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