JPH05129948A - Pll circuit - Google Patents

Abstract

PURPOSE:To make the action of a VCXO circuit stable by interrupting a reference input clock and latching the output of a sample-hold circuit, thereby closing a gate circuit and freezing other components than the VCXO in a state just before the clock interruption. CONSTITUTION:When a reference input clock 14 is inputted, an interruption detection circuit 19 does not detect clock interruption and a control circuit 20 brings a sample-hold circuit 18 and a gate circuit 12 into a through-state. When the clock 14 is interrupted, the circuit 19 is activated and the circuit 20 latches the output of the circuit 18 and closes the circuit 12 to stop the clock input to a frequency divider circuit 13 and stops the action. Thus, all circuit components other than a VCXO 11 are held in the sate just before the interruption of the clock 14. When the clock 14 is restored from the interruption, the fixing state is released and the state is restored to the state just before the input interruption of the clock 14. Thus, a sudden change in the oscillating frequency and the phase of the VCXO is prevented before and after the process of a loss of the reference input clock to make the oscillation circuit stable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit in a transmission device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a PLL circuit of this type has a VCXO 51, a first frequency dividing circuit 53 having an output of the VCXO 51 as an input, and a second input circuit 54 having a reference input clock 54 as an input. Frequency dividing circuit 55 and the first frequency dividing circuit 5
3 and the output of the second frequency dividing circuit 55 as inputs, and a filter circuit 57 that receives the output of the phase comparing circuit 56 as an input and the output of which is connected to the voltage control input of the VCXO 51. And had.

The PLL circuit shown in FIG.
CXO 51, first frequency divider circuit 53, phase comparison circuit 56,
Through the automatic control system by the feedback loop formed by the filter circuit 57, it operates in frequency and phase synchronization with the reference input clock 54.

[0004]

In this conventional PLL circuit, the force of the phase comparison circuit 56 changes when the reference input clock 54 is cut off and when it is restored from the cutoff.
The VCXO 51 power fluctuates, and there is a problem in that the transmission device is erroneously operated especially when this change is large. Such a pattern is shown in FIG.

[0005]

An object of the present invention is to improve the inconvenience of the conventional example, and in particular, it is possible to effectively ensure the stable operation of the VCXO oscillation circuit even if the clock of the reference clock sent from the outside is interrupted. Its purpose is to provide a circuit.

[0006]

According to the present invention, a VCXO oscillation circuit and a first input for inputting an output of the VCXO oscillation circuit.
Frequency divider circuit, a second frequency divider circuit for inputting a reference clock sent from the outside, a phase comparator circuit for inputting the outputs of the first and second frequency divider circuits, and And a filter circuit for receiving the output of the phase comparison circuit and outputting a predetermined control voltage for the VCXO oscillation circuit. The input circuit of the first frequency dividing circuit is equipped with a gate circuit which operates as required. A sample and hold circuit is provided between the filter circuit and the VCXO oscillator circuit. In addition, a clock break detection circuit is provided to detect the reference clock sent from the outside immediately when it becomes disconnected, and a gate circuit and sample and hold circuit are provided according to the output signal from this clock break detection circuit. The configuration is such that a control circuit for drive control is provided. This aims to achieve the above-mentioned object.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The embodiment shown in FIG. 1 is a VCXO oscillator circuit 1.
1 and the first that inputs the output of this VCXO oscillation circuit 11
Frequency dividing circuit 13, a second frequency dividing circuit 15 for inputting a reference clock sent from the outside, and a phase comparison for inputting outputs of the first frequency dividing circuit 13 and the second frequency dividing circuit 15. The output of the circuit 16 and the phase comparison circuit 16 is input to VCX
The filter circuit 17 outputs a predetermined control voltage for the O oscillator circuit 11. The input stage of the first frequency dividing circuit is equipped with a gate circuit 12 that operates as needed. In addition, the filter circuit 17 and the VCXO oscillation circuit 11
A sample and hold circuit 18 is provided between and. Further, there is provided a clock break detection circuit 19 for immediately detecting when a reference clock sent from the outside is in a cut state, and the gate circuit 12 and the sample circuit are provided in response to an output signal from the clock break detection circuit 19. A control circuit 20 for driving and controlling the hold circuit 18 is provided. Then, the control circuit 20 has a normal operation freezing function that operates immediately when the clock break detection signal from the clock break detection circuit 19 is input, sets the sample and hold circuit 18 in the latched state, and closes the gate circuit.

Next, the operation of the above embodiment will be described. Figure 1
In the above, when the reference input clock 14 is input, the disconnection detection circuit 19 does not detect the clock disconnection. At this time, the control circuit 20 controls the sample and hold circuit 18 and the gate circuit 12 to be in the through state. At this time, the PLL circuit of FIG. 1 operates in the same manner as the conventional PLL circuit of FIG.

When the reference input clock 14 is disconnected, the disconnection detection circuit 19 operates, and the control circuit 20 receives this output and latches the output of the sample and hold circuit 18, and further closes the gate circuit 12 to close the first circuit. The clock input to the frequency dividing circuit 13 is stopped, and the operation of the first frequency dividing circuit 13 is stopped. As a result, in the PLL circuit of FIG. 1, all parts except the VCXO 11 are frozen in the state immediately before the disconnection of the reference input clock 14. When the reference input clock 14 recovers from the interruption, the frozen state is released and the PLL returns to the state immediately before the interruption of the reference clock 14. Therefore, the reference input clock 1
It is possible to prevent a sudden change in the oscillation frequency and phase of the VCXO 11 before and after the disappearance process of No. 4 described above.

[0010]

As described above, according to the present invention, when the reference input clock is cut off, the output of the sample and hold circuit is latched, and the gate circuit is closed to set VC.
Since all parts except the XO oscillator circuit are frozen in the state immediately before the interruption of the reference input clock, it is possible to effectively prevent sudden changes in the oscillation frequency and phase of the VCXO oscillator circuit before and after the process of disappearing the reference input clock. It is possible to provide an excellent PLL circuit that is not possible in the past.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is an explanatory diagram showing an operation example of FIG.

[Explanation of symbols]

 11 VCXO oscillator circuit 12 gate circuit 13 first frequency divider circuit 14 reference input clock 15 second frequency divider circuit 16 phase comparator circuit 17 filter circuit 18 sample and hold circuit 19 clock loss detection circuit 20 control circuit

Claims (2)

[Claims] 1. A VCXO oscillator circuit, a first frequency divider circuit for inputting the output of the VCXO oscillator circuit, a second frequency divider circuit for inputting a reference clock sent from the outside, and the first frequency divider circuit. A phase comparison circuit for inputting the outputs of the frequency division circuit and the second frequency division circuit, and an input of the output of this phase comparison circuit for the V
In a PLL circuit including a filter circuit for outputting a predetermined control voltage for a CXO oscillation circuit, a gate circuit that operates as necessary is provided in an input stage of the first frequency dividing circuit, and the filter circuit and the VCXO are provided. A sample and hold circuit is provided between the oscillator circuit and a clock break detection circuit that immediately detects when the reference clock sent from the outside is cut off. A PLL circuit comprising a control circuit for driving and controlling the gate circuit and the sample and hold circuit according to an output signal. 2. The control circuit has a normal operation freezing function that operates immediately upon input of a clock loss detection signal from the clock loss detection circuit, sets the sample / hold circuit in a latched state, and closes the gate circuit. The PLL circuit according to claim 1, wherein the PLL circuit is provided.