JP3315305B2 - Horizontal synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal oscillation circuit for a TV signal processing IC and a horizontal synchronization circuit for stabilizing a horizontal output signal.

[0002]

2. Description of the Related Art A conventional horizontal synchronizing circuit will be described with reference to FIG. Synchronization separation circuit 1 from input video signal
01 separates the synchronization signal. The phase of the output of the sync separation circuit 101 and the phase of the output of the horizontal oscillation circuit 104 are compared by a phase comparison circuit 102. The output of the phase comparison circuit 102 is smoothed by a smoothing circuit 103, and this output is
4 is controlled.

As described above, the output of the horizontal oscillation circuit 104 is fed back to the phase comparison circuit 102, whereby the output of the horizontal oscillation circuit 104 and the phase of the synchronization signal are locked. That is, the horizontal synchronization circuit has a general PLL configuration. Here, the horizontal oscillation circuit 10 used for the horizontal synchronization circuit is used.
Reference numeral 4 denotes a voltage controlled oscillation circuit whose frequency is generally controlled by the output voltage of the smoothing circuit 103. Therefore H-VC
Called O. However, in this case, since the oscillation circuit uses the resonator 105 called CERALOCK and uses the resonance frequency as a reference, it is originally a resonance frequency reference voltage controlled oscillation circuit (VCXO).

A conventional horizontal oscillation circuit includes an external resonator 1
At 05, the oscillation frequency and the horizontal output were stabilized. For this purpose, a dedicated pin of the resonator 105 is required for the IC. However, a signal with a strong radio power such as an illegally modified amateur radio radio jumps into a dedicated pin, and as a result, the horizontal frequency fluctuates, and in the worst case, the TV set may be destroyed. Therefore, although not shown in FIG. 10, a circuit for protecting the set and the IC is required, and the cost is increased together with the external resonator 105.

[0005]

As described above, the conventional horizontal synchronizing circuit not only requires an external resonator and a dedicated pin when it is integrated into an IC, but also requires measures against illegal radio.

The present invention provides a horizontal synchronization circuit that does not require an external resonator.

[0007]

In order to solve the above-mentioned problems, a horizontal synchronization circuit according to the present invention is included in a video signal.
A synchronization separation circuit for separating a synchronization signal, and the synchronization separation circuit
Phase that compares the phase of the synchronous output of the
A comparison circuit, and a first circuit for smoothing an output of the phase comparison circuit.
The oscillation frequency of the output of the smoothing circuit and the first smoothing circuit is
The horizontal oscillation circuit to be controlled,
A first control for matching the frequency of the path with the phase of the synchronization signal
Control loop, the frequency of the reference signal and the output of the horizontal oscillation circuit.
A frequency comparing circuit for comparing force frequencies; and
The frequency of the reference signal and the horizontal oscillation
Synchronous detection circuit that detects that the circuit output frequencies match
And a second smoothing unit for smoothing the output of the frequency comparison circuit.
Circuit, an output of the second smoothing circuit, and the first smoothing circuit.
A summing circuit for adding the outputs of the roads,
Second control for automatically adjusting the free-running frequency of the oscillation circuit
A loop, the first control loop and the second control loop.
Controls not to operate at the same time,
Operate the second control loop within the vertical blanking period
And control means .

With this configuration, the synchronization signal and the phase of the horizontal oscillation circuit are synchronized by the first control loop,
With the control loop described above, the frequency of the horizontal oscillation circuit can be automatically adjusted to a desired frequency with reference to the frequency of the reference signal. Therefore, since the horizontal oscillation circuit does not require a resonator, the circuit can be completely built in an IC.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention. A synchronization signal of a video signal is separated by a synchronization separation circuit 1.
The phase of the output of the synchronization separation circuit 1 and the output d1 of the frequency dividing circuit 15 for dividing the output of the horizontal oscillation circuit 7 are compared by the phase comparing circuit 6. This phase comparison circuit 6 can change the detection sensitivity of the phase comparison with the key pulse KP1. The output of the phase comparison circuit 6 is smoothed and output by the smoothing circuit 3 via the switch 12 for controlling conduction / non-conduction. The output of the smoothing circuit 3 and the output of the smoothing circuit 11 are added by an addition circuit 14. The horizontal oscillation circuit 7 whose frequency is controlled by the output of the addition circuit 14 constitutes a first control loop CL1.

During the period of the key pulse KP2, the frequency of the reference signal 8 and the frequency of the output d2 of the frequency dividing circuit 15 are compared and output by the frequency comparing circuit 9 while corresponding to a vertical system. From the output of the frequency comparison circuit 9, the synchronization detection circuit 10 detects whether or not the frequency of the reference signal 8 matches the frequency of the output d2 of the frequency division circuit 15. The switch 13 is turned on / off by the output of the frequency comparison circuit 9. The output of the switch 13 is smoothed by the smoothing circuit 11. By inputting the output of the smoothing circuit 11 to the horizontal oscillation circuit via the addition circuit,
A second control loop CL2 is configured.

The first control loop CL1 synchronizes the synchronization signal with the phase of the horizontal oscillation circuit 7, and the second control loop C1
L2 performs an automatic frequency adjustment operation for setting the frequency of the horizontal oscillation circuit 7 to a desired frequency based on the frequency of the reference signal 8.

Next, the operation of FIG. 1 will be described. First,
It is assumed that the switch 12 is closed, the switch 13 is opened, and the key pulse KP2 is not input. The operation under this condition is the same as the operation of a general horizontal synchronization circuit, and will be described from this operation.

An input video signal is input to a sync separation circuit 1. The synchronization separation circuit 1 separates a synchronization signal included in the input video signal, and inputs the synchronization signal to one side to the phase comparison circuit 6.
The output d1 of the frequency divider 15 is connected to the other input of the phase comparator 6, and the phase comparator 6
Is output to the smoothing circuit 3. The output of the smoothing circuit 3 is added to the addition circuit 14
, The oscillation frequency of the horizontal oscillation circuit 7 becomes a frequency synchronized with the synchronization signal.

As described above, the oscillation frequency fHvco of the horizontal oscillation circuit 7 is fHvco = nfH. Here, fH is the horizontal frequency.

Incidentally, the frequency dividing circuit 3 is one in which what is generally called H countdown and V countdown is integrated.

Next, when the switch 12 is open, the switch 1
The case where 3 is closed will be described. In this switching state, the oscillation frequency of the horizontal oscillation circuit 7 is automatically adjusted.

The frequency of the output d2 of the frequency dividing circuit 15 and the frequency of the reference signal 8 are compared by a frequency comparing circuit 9. The key pulse KP2 is a pulse for limiting the operation time of the frequency comparison circuit 9. Here, it is assumed that the frequency comparison circuit 9 operates when the key pulse KP2 is Hi. The second output of the frequency comparison circuit 9 is input to the smoothing circuit 11 via the switch 13. The output of the smoothing circuit 11 is
4 to a horizontal oscillation circuit 7. With the above loop configuration, the oscillation frequency of the horizontal oscillation circuit 7 can be adjusted to a desired frequency based on the frequency of the reference signal 8.

The operation of the two loops described above is summarized as follows.

First, the frequency of the horizontal oscillation circuit 7 is adjusted to a desired frequency by the automatic adjustment loop of the horizontal oscillation circuit 7. Here, the synchronization detection circuit 10 determines whether or not the frequency of the horizontal oscillation circuit 7 is a desired frequency. If the automatic adjustment is completed, the switch 12 is closed and the switch 13 is opened. As a result, the voltage at the end of the automatic adjustment is held in the smoothing circuit 11. Therefore, the frequency of the horizontal oscillation circuit 7 continues to oscillate at a frequency determined by the voltage held in the smoothing circuit 11.

Therefore, the horizontal synchronization circuit starts operating based on the fixed oscillation frequency of the horizontal oscillation circuit 7. Then, the frequency of the horizontal oscillation circuit 7 is pulled down to a frequency synchronized with the synchronization signal from the operation of the horizontal synchronization circuit. Therefore, the output of the addition circuit 14 is the sum of the automatic adjustment voltage of the output of the smoothing circuit 11 and the phase difference detection voltage of the horizontal synchronization circuit generated at the output of the smoothing circuit 3, and the frequency of the horizontal oscillation circuit 7 is automatically adjusted. Based on the adjustment voltage, the voltage corresponds to the phase difference detection voltage of the horizontal synchronization circuit.

From the above description, it can be seen that the desired horizontal oscillation circuit 7
The frequency at the end of automatic adjustment (hereinafter, center frequency) is
It can be seen that it is better to be as close as possible to the frequency shown in equation (1).

Hereinafter, each circuit of this embodiment will be described with reference to the drawings. First, the relationship between the phase comparison circuit 6 and the key pulse KP1 will be described with reference to FIG. Generally, the phase comparison circuit 6 is configured by a multiplication circuit, for example, using a double balance circuit. The time constant of the synchronization detection of the horizontal synchronization circuit using this circuit is determined by the time constant of the smoothing circuit 3 and the current flowing through the phase comparison circuit 6 in the figure. When the time constant determined by the relationship between the current and the smoothing circuit 3 is long, the synchronization detection time is long, and when the time constant is short, the synchronization detection period is short.
Generally, this time constant is set to approximately 40 ms. Therefore, when there are two states of the automatic adjustment state and the operation state of the horizontal synchronization circuit as in this embodiment, the synchronization pull-in time of the horizontal synchronization circuit is the center of the horizontal oscillation circuit 7 after the automatic adjustment is completed. It may be slow depending on the frequency. Then, after the automatic adjustment of the horizontal oscillation circuit 7 is completed, the above problem may be dealt with by shortening the synchronization pull-in time of the horizontal synchronization circuit for a certain period. Here, in this embodiment, the time constant is shortened by increasing the current of the phase comparison circuit 6 with respect to the normal period during the period determined by the key pulse KP1, thereby shortening the synchronization pull-in time of the horizontal synchronization circuit.

Next, the frequency comparison circuit 9 will be described with reference to FIGS. The frequency comparison circuit 9 is configured by a pulse count method. The frequency comparison circuit 9 includes a counter 31 and a decoding circuit 32 as shown in FIG. The operation will be described below with reference to FIG.

Masking the pulse B with the key pulse KP2,
Make pulse C. By setting / resetting the counter 31 with the pulse C, the operation period of the counter 31 is controlled. The pulse A is a count pulse of the counter 31. With this configuration, the number of pulses A is counted while the pulse C is Hi, and the result is transmitted to the next decoding circuit 3.
Output to 2.

The decoding circuit 32 detects whether the relationship between the pulse A and the pulse B has a desired frequency relationship from the output of the counter 31. That is, when the detection result is higher than the desired frequency, the output A is set to Hi and the output B is set to L
ow. When the frequency is lower than the desired frequency, the output A is set to Low and the output B is set to Hi. Further, when the counter output indicates a desired output, both outputs A and B are set to be low.

Here, it is apparent from the operation of the frequency comparison circuit 9 that if the pulse A is used as the reference signal, the pulse B becomes the second output d2 of the frequency dividing circuit. If it is the second output, pulse B will be the reference signal. In either case, the detection operation of the decoding circuit 32 is established so that the frequency discrimination result can be accurately output to the next-stage smoothing circuit 11 in any state. The system control pulse input to the decoding circuit 32 enables an output corresponding to the difference between the vertical 50 Hz / 60 Hz system to be obtained. Although not shown, the reference signal 8 is generated using an oscillation circuit for color demodulation.

Next, the synchronization detecting circuit 10 will be described.
As shown in FIG. 5, the synchronization detection circuit 10 includes a NOR gate 5
1 and an inverter 52. The synchronization detection circuit 10 is a circuit for detecting whether or not the pulses A and B shown in FIG. 3 are synchronized, in other words, a circuit for detecting whether or not the automatic adjustment is completed.

Therefore, if the outputs A and B of the decoding circuit 32 are both Low, the pulses A and B are synchronized. Based on the above results, the switch 1 shown in FIG.
2 and 13 are controlled. Here, by using the output of the NOR gate 51 for controlling the switch 12 and using the output of the inverter 52, which is the inverted output of the NOR gate 51, for controlling the switch 13, the switch 12 is closed when the automatic adjustment is completed. The switch 13 is opened to operate the horizontal synchronization circuit.

Next, the smoothing circuit 11 of FIG. 1 will be described with reference to FIG. The smoothing circuit 11 increases the outputs A and B of the frequency comparison circuit 9 and the up / down control pulse generated at the timing shown in FIG. 4 via a logic circuit using two NAND circuits 61 and 62 shown in FIG. -Input to the down counter 63. Further, the up / down counter 63 performs the down / up control at the falling timing of the up / down control pulse when the frequency is high or low by the input pulse, and the D / A converter 64 outputs the output of the up / down counter 63 Is controlled by The control using the up / down counter 63 realizes a time constant equivalent to a time constant obtained by using a general filter.

In this embodiment, an automatic adjustment circuit using a frequency comparison circuit 9, a synchronization detection circuit 10, and a smoothing circuit 11 and a phase comparison circuit 6 capable of switching the detection speed by a key pulse KP2 are used. The frequency of the horizontal oscillation circuit 7 becomes exactly the desired frequency, and the operation of the horizontal synchronization circuit after the automatic adjustment ends quickly becomes stable. Further, each pulse shown in FIG. 4 is within the vertical blanking, and it is considered that various processes do not affect the video displayed on the TV.

FIG. 7 is a circuit diagram for explaining a second embodiment of the present invention. In this embodiment, FIG.
Switch 13 of the second control loop CL2 of the embodiment
Is deleted, and the key pulse KP2 is input to the synchronization detection circuit 10, and the key pulse KP2 is input to the frequency comparison circuit 9 via the synchronization detection circuit 10.

If the outputs A and B of the frequency comparison circuit 9 and the smoothing circuit 11 described in FIG. 3 are also applied to the embodiment described here, if the frequency of the horizontal oscillation circuit 7 has a desired value. , The output of the smoothing circuit 11 does not change. Therefore, it is not necessary to control the input of the smoothing circuit 11 by the output of the synchronization detection circuit 10, so that the switch 13 shown in FIG. 1 is not required.

The synchronization detection circuit 10 shown in FIG. 7 will be described more specifically with reference to FIG. The frequency comparison circuit 9 described above
Are output to a set terminal S of a latch circuit 82 composed of an RS-FF via a NOR circuit 81. Further, a POR (power-on-reset) pulse required when power is turned on is input to the reset terminal R of the latch circuit 82. The output of the latch circuit 82 is connected to a NAND circuit 83
, And the above-described key pulse KP2 is input to the other input terminal via the inverter 84. The output b of the NAND circuit 83 is used as the key pulse KP2 of the frequency comparison circuit 9,
The output a via 5 is used to control the switch 12 of FIG.

Each timing of the synchronization detection circuit 10 is
This will be described with reference to the timing chart of FIG. When the power is turned on, the latch circuit 82 is reset by the POR pulse, so that the output Q is low. Therefore, regardless of the state of the key pulse KP2, the output a of the synchronization detection circuit 10 is always low and the output b is always high. As a result, the switch 12 shown in FIG. 7 is always open, and the horizontal synchronization circuit does not operate. That is, the automatic adjustment state is always established regardless of the key pulse KP2. Thereafter, when the automatic adjustment is completed and the latch circuit is set, the output Q of the latch circuit becomes Hi, so that the output of the synchronization detection circuit 10 becomes an output synchronized with the key pulse KP2. With this control,
When the power is turned on, the automatic adjustment mode is set for the entire period, so that the automatic adjustment ends immediately.

As described above, the synchronization detection circuit 10 operates only when the power is turned on or when the power is once turned off for some reason, and the switch 12 is opened until the first automatic adjustment is completed. The state is maintained, and then the opening / closing is controlled by controlling the key pulse KP2. In fact, it is considered that the self-running frequency of the automatically adjusted horizontal oscillation circuit 7 is farthest from the desired frequency when the power is turned on.
It is considered that once the automatic adjustment is completed after the injection, the oscillation will continue at a substantially desired frequency after that, although there is a self-running frequency deviation due to temperature drift or the like. Therefore, it is considered that the control of the key pulse KP2 is sufficient without depending on the output of the synchronization detection circuit 10.

As described above, in the case of the embodiment shown in FIG. 7, in a transitional state such as when the power is turned on, the entire automatic adjustment period is set until the first automatic adjustment is completed. After the automatic adjustment is completed, the automatic adjustment is performed within the vertical blanking period as described above. At this time, the switching between the automatic adjustment operation and the operation of the horizontal synchronization circuit is performed only by the control of the key pulse KP2 without depending on the output of the synchronization detection circuit.

In each embodiment of the present invention, all the circuits constituting the automatic adjustment circuit are constituted by digital circuits except for the D / A converter. However, it is possible to realize the above contents even with a configuration using an analog circuit.

[0038]

As described above, the horizontal synchronizing circuit according to the present invention does not require a resonator for generating a reference signal, so that it is possible to realize a built-in IC. As a result, it is possible to prevent the set from being destroyed by illegal radio without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a relationship between the phase comparison circuit of FIG. 1 and a key pulse.

FIG. 3 is a circuit diagram for explaining the frequency comparison circuit of FIG. 1 more specifically;

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a circuit diagram for explaining the synchronization detection circuit of FIG. 1 more specifically;

FIG. 6 is a circuit diagram for more specifically explaining the smoothing circuit of FIG. 1;

FIG. 7 is a circuit diagram for explaining a second embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining the synchronization detection circuit of FIG. 7 more specifically;

FIG. 9 is a timing chart for explaining the operation of FIG. 8;

FIG. 10 is a circuit diagram for explaining a conventional horizontal synchronization circuit.

[Explanation of symbols]

CL1: first control loop, CL2: second control loop, 1: synchronization separation circuit, 3: smoothing circuit 1, 6: phase comparison circuit, 7: horizontal oscillation circuit, 8: reference signal, 9: frequency comparison circuit , 10: synchronization detection circuit, 11: smoothing circuit, 12,
13: switch, 14: addition circuit.

Claims (5)

(57) [Claims] 1. A synchronization separation circuit for separating a synchronization signal included in a video signal, a phase comparison circuit for comparing a synchronization output of the synchronization separation circuit with a phase of an output of a horizontal oscillation circuit, and an output of the phase comparison circuit. includes a first smoothing circuit for smoothing, and said horizontal oscillation circuit whose oscillation frequency is controlled by the output of said first smoothing circuit, the first to match the phase of the frequency and the synchronizing signal of the horizontal oscillator circuit And a frequency comparison circuit that compares the frequency of the reference signal with the output frequency of the horizontal oscillation circuit, and that the output of the frequency comparison circuit matches the frequency of the reference signal with the output frequency of the horizontal oscillation circuit. a synchronization detection circuit for detecting a second smoothing circuit for smoothing the output of said frequency comparison circuit, and addition circuit adding the outputs of said first smoothing circuit of the second smoothing circuit A, wherein a second control loop for the free-running frequency of the horizontal oscillation circuit for automatically adjusting, together with the first control loop and said second control loop is controlled not to operate simultaneously, the second Control of
Control means for operating the loop during a vertical blanking period . 2. The apparatus according to claim 1, further comprising first and second switches for performing ON / OFF control of said first and second control loops based on an output of said synchronization detection circuit. Horizontal synchronization circuit. 3. The synchronous detection circuit determines a transient state and a steady state at the time of power- on, and determines the second control circuit.
The horizontal synchronization circuit according to claim 1, further comprising a function of operating the loop even in the transition state . 4. Corresponding to the broadcasting system, the horizontal synchronizing circuit according to claim 1, characterized by further comprising a frequency comparator circuit for controlling the output frequency of the horizontal oscillator. Wherein when switching to the first control loop, the time constant of the synchronous detection in the first control loop
The horizontal synchronizing circuit according to claim 1, further comprising a switch for shortening a period from a steady state during a predetermined period .