JPS62268274A - Horizontal synchronism reproducing circuit - Google Patents

Abstract

PURPOSE:To facilitate the execution of fine adjusting of the output phase and frequency of a horizontal oscillation counter circuit by constituting a horizontal synchronizing circuit with digital circuits, and delaying the counting clock by the action of a delay circuit. CONSTITUTION:At a point of time, the counting value of the horizontal oscillation counter circuit 6 is determined, when the input to the delay circuit 7 is selected and the cycle shifts to a horizontal synchronizing period, a delay amount control circuit 8 selects the output (R) of a unit delay buffer circuit 301. Further, at the point of shifting to the following horizontal synchronizing period, the circuit 8 selects the output (C) of a unit delay buffer circuit 302, and thereafter, the said selection shifts sequentially from (C) to (D), and from (i) to (j). When the selection com/s to the last (j), it returns to the (A), and the above mentioned action is repeated. In such a way, the counting clock frequency is var ed by phase-shifting the counting clocks o.1 clock per one horizontal period, and consequently, the horizontal oscillation frequency is varied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital television receiver, which is a horizontal receiver suitable for digital signal processing of a non-standard television signal in which the burst signal frequency and the horizontal synchronization signal frequency do not have a sufficient relationship. This invention relates to a synchronous reproduction circuit.

6→Hikari→Hori-1'4-4-=e C Wandering→No, 4
M71 A television receiver using the conventional ateroglyff-1 processing method (the problem of sieving image quality that was difficult with giso, that is,
In order to solve the problem of improving performance such as brightness and color signal separation, synchronization performance, etc., as well as the problem of component variations due to analog parts, digital television is a digital television that processes everything after the video stage of the television receiver. Jinjin reception is being considered. In such digital television receivers, the four arithmetic circuits are also digitized.
A conventional example is JP-A No. 59-50669. 8th
The figure shows a conventional example, in which 801 is a 4/Z) converter for digitizing a video signal, 802 is a synchronization separation circuit for obtaining a synchronization signal from the video signal, 803 is a phase m-wave circuit, and 804 805 is a loop filter, 805 is an oscillation circuit composed of a counter circuit, 806 is an M extension circuit for finely adjusting the cabal phase of 805, 807 is a horizontal drive circuit, 808 is a horizontal output circuit, and 809 is a comparison signal generation circuit.

Referring generally to FIG. 8, the video signal is digitized by a converter 801 and applied to a sync separator circuit 802 to pass horizontal sync pulses. On the other hand, the horizontal output circuit 808
The output pulse, for example, a horizontal flyback pulse, is integrated by a comparison signal generation circuit 809, and inputted together with the horizontal synchronizing pulse to a phase counting circuit 803, where a phase comparison of both pulses is performed and a phase error of each number is obtained. . The phase error signal is averaged by a loop filter 804, and this signal is used as a control signal to control the horizontal oscillation frequency and phase of the oscillation circuit 805 to match the input horizontal synchronizing signal. On the other hand, a part of the output of the loop filter 804 is used to control the amount of delay of the delay circuit 806 to finely adjust the phase of the horizontal synchronization signal. The output of this delay circuit 806 passes through a horizontal drive circuit 807 and a horizontal output circuit 808 to become a horizontal deflection output.

The pLL (phase locked loop) circuit V as described above has a disadvantage in that stable operation cannot be performed due to the horizontal oscillation local wave number and phase control input.

Now, the counting clock frequency f input to the oscillation circuit 805
, is selected as l5-4 fsc (fsc: color subcarrier frequency), and if an NTSC signal is input, there is normally a relationship of fs = 910fx (fx: horizontal synchronization frequency of input video signal). However, VTR'
This relationship may not hold true for video signals such as F game machines. For example, if the relationship is fs=91t4fI, then in the above oscillation circuit 705,
After the counting clock is counted down by 911 and a horizontal synchronizing signal is generated, the signal is delayed by a delay circuit 806 to perform fine adjustment.

In this way, oscillation circuit 8050 countdown number = 911
If the delay circuit 806 is fixed to , and later fine adjustment is performed only by the delay circuit 8o6, the delay cap of the delay circuit 806 will be accumulated as shown in the waveform diagram of FIG. Here, (α) in Figure 9
is obtained by the synchronization separation circuit 802. Also,
FIG. 9 (bl is the oscillation start (or end) position of the oscillation circuit 805, and (cl is the horizontal oscillation output waveform H1 finely adjusted by the delay circuit 806. In FIG. 9, the waveform (α) and ( C) They are brought together at a certain time T. At this time, since the delay amount of the delay circuit 806 = 0, the horizontal synchronization signal H
, and the horizontal oscillation output signal HD is output after a period of 10τ).

However, even here, a phase error signal H1 is obtained between the horizontal synchronization signal H and the horizontal oscillation output signal 89. However, at this time, the phase error between the horizontal synchronization signal H and the water oscillation output signal HD becomes 2τ. Since phase errors are accumulated one after another in this way, an infinite amount of delay is required as the delay amount of the delay circuit 806. Furthermore, when this phase error becomes equal to or more than 1Ω of the counting clock given to the oscillation circuit 805, the count value of the oscillation circuit 805 may be changed; however, if this is done, the delay circuit 806 The delay amount is also reset, resulting in jitter in horizontal oscillation.

As described above, in the conventional example, the delay amount of the delay circuit for fine adjustment of horizontal oscillation must be infinite, or even if the delay amount is finite, jitter will occur in the horizontal oscillation output. was there.

The purpose of the present invention is to improve the above-mentioned drawbacks of the conventional device, to improve synchronization accuracy, and to use digital signal processing, which requires relatively small scale. The object of the present invention is to provide a synchronous reproduction circuit.

In the present invention, in order to achieve the above object, the delay circuit for fine adjustment of the horizontal synchronous oscillation frequency in the conventional example is installed in front of the oscillation circuit.
The frequency of the counting clock can be adjusted by freely delaying the counting clock from the VCO within one clock period as necessary, and this finely tuned counting clock can be used by the next stage oscillation circuit. By tuning down, a reproduced horizontal synchronizing signal with stable oscillation frequency and phase can be obtained.

[Example of beak poison]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram schematically showing a horizontal synchronization reproducing circuit according to the present invention. In the figure, 1 is an A/1) converter that converts a baseband analog video signal -Q into a digital video signal, 21 is a burst extraction circuit that extracts a burst signal from the output video signal of the ω converter 1, and 22 is an A/1 converter that converts a baseband analog video signal -Q into a digital video signal. The burst signal obtained by the burst extraction circuit 21 and 4 fsc (f
sc: A phase detection circuit that generates a control signal by comparing the phase with the fsc signal obtained by dividing the color subcarrier frequency by 4 using a frequency divider 3. 4 is an analog output control signal of the phase detection circuit 22. 6 is a horizontal oscillation counter circuit that generates horizontal drive pulses; 7 is a delay circuit for finely adjusting the frequency and phase of the counting clock supplied to horizontal oscillation counter circuit 6; 8 is a delay circuit 7 a delay amount control circuit for controlling the delay amount; 9 a decoder circuit for giving a preset value to the counter circuit section in order to control the count value of the horizontal launch counter circuit 6;
10 is a loop filter with a time constant of several 10:/'', (T, : horizontal scanning period), and 11 is a synchronization separator that separates the horizontal synchronization signal and vertical synchronization isa signal from the output digital video signal of the A/D converter 1. 12 is a phase detection circuit that compares the phase of the horizontal synchronous signal 4B obtained by the synchronous separation circuit 11 and the output signal of the integrator 15 and generates a control signal; 14 is a horizontal signal output from the horizontal oscillation counter circuit 6; A horizontal drive circuit 15 driven by a drive pulse is a horizontal output circuit that amplifies the output of the horizontal drive circuit 14 and outputs a horizontal deflection pulse.

Next, the operation of FIG. 1 and details of each part will be explained.

The part 7A in FIG. 1 corresponds to a part that generates a signal for color demodulation in a conventional analog television receiver and a phase detection circuit part that synchronizes the generated clock with the burst. In this embodiment, the sampling clock frequency a of the A/D converter 1 is a=4 jsc (f
a, c: color subcarrier frequencies). Therefore, the oscillation frequency of VCO5 is also pLL as 4 fIC.
It constitutes a circuit. First, from the video signal digitized by the A/D converter 1, only the burst signal is extracted by the burst extraction circuit 21, and the phase is compared with the clock frequency divided by 4 by the divider 3 by the phase detection circuit 22. Obtain phase error signal 2. This phase error signal is further transmitted to the phase detection circuit 22.
The output signal is averaged by a loop filter in the inner loop filter, and the excavation frequency of the VCO 5 is controlled as an analog control voltage by the D/A converter 4, thereby obtaining a clock synchronized with the burst signal. The above is an outline of the clock generating section A.

Next, the horizontal synchronizing signal reproducing section H will be explained. , the digital video signal from the Φ converter 1 is input to a synchronization separation circuit 11 to obtain a horizontal synchronization signal H0 and a vertical synchronization signal 6. On the other hand, a horizontal output pulse from the horizontal output 16, for example a horizontal flyback pulse H! B is integrated by the integrating circuit 13, and in addition to the phase detection circuit 1Nr12, the horizontal synchronization circuit 4g I
A comparison signal with I is obtained. This situation is shown in the waveform diagram of FIG. Although FIG. 2 shows analog waveforms to illustrate the concept of operation, in reality everything is digital. Figure 2 (1) shows the horizontal synchronization 18 +=iIiy of the output of the synchronization separation circuit 11; (2) shows the horizontal flyback pulses H and β from the horizontal output circuit; The comparison signal α is integrated by 13, and the horizontal synchronization signal '@ Buddha and the comparison signal α are input to the phase detection circuit 12 and phase comparison is performed, as shown in Fig. 2 (4).
Obtain the detection output of The detected output signal is converted into a direct current signal by the loop filter 10 to obtain the control signal C shown in FIG. 2 (5). The reproduction horizontal synchronization frequency is controlled by this control value +8-c. This control method will be explained below.

The control signal C in FIG. 2 (5) is a digital signal, which is divided into upper focus and lower bits, and the lower bit side is sent to the delay amount control circuit 8 which controls the delay amount of the delay circuit 7. , upper pin) iIIIH and are respectively applied to a decoder circuit 9 that controls the oscillation frequency of the horizontal oscillation counter circuit 6 . FIG. 3 is a diagram showing details of the horizontal synchronous reproducing section surrounded by the broken line B in FIG. 1, particularly the delay circuit 7 and the decoder circuit 9.

In the figure, 601 to 609 are buffer circuits having a unit delay amount, 610 to 619 are HAND circuits for selecting the delay amount, and 3
Reference numeral 20 denotes a NAND circuit that outputs a counting clock whose frequency and phase have been adjusted by delay, and the delay circuit 7 is configured by the above. Further, the decoder circuit 9 includes a latch circuit 621, an addition/subtraction circuit 322, a switch 525, and a zero discrimination circuit 324.

Further, 325 controls the clock with an AND circuit.

In addition, the same numbers as in Figure 1 refer to Zhanglong.

First, to explain the operation of the decoder circuit 9, in an initial state (for example, when the system power is turned on), a set pulse (for example, a defeat pulse for muting an audio signal) is applied to the latch circuit 321, and the preset 1 pulse is applied to the latch circuit 321. This preset value given is that the VTR video No. 45 has an NTSC signal (counting clock frequency f,
Considering that the signal satisfies the relationship of = 91o f, fH: horizontal periodic frequency), it fluctuates by ±10 degrees, and the resulting horizontal synchronization frequency that is reproduced is set to a value that is sufficiently high, for example, 2.
(However, it is assumed that the horizontal oscillation counter circuit 6 is reset at a 10-stage counter, that is, 2'' = 1024 counts.) From this i[, the horizontal oscillation counter circuit 6 counts a predetermined number of clocks. , a horizontal excavation output is obtained.In the next horizontal period, the output of the latch circuit 621 and the control signal consisting of the upper bits of the loop filter 10 are added or subtracted by the adder/subtracter circuit 322 according to the sign bit of the loop filter 10. to latch and obtain a new preset value.

Here, the latch clock of the latch circuit 621 is the flyback pulse H! from the horizontal output circuit 15! Input one horizontal period clock such as B. Thereafter, this operation is repeated sequentially, and when the horizontal oscillation frequency converges to a predetermined value, the control data of the loop filter 10 becomes zea, and the zero discrimination circuit 324
operates, the switch 323 opens, and the latch circuit 321 holds the preset value at that time.

Rough horizontal oscillation control is performed through the above operations. Next, a method for finely adjusting the frequency and phase of horizontal oscillation will be described below with reference to FIG.

Unit delay buffer circuit 30 in delay circuit 7 in FIG.
It is assumed that the unit delay amount from 1 to 309 is 01 clock cycles and the total delay amount is 09 clock cycles. At this time, the output clock waveforms of the unit delay buffer circuits 601-309 correspond to (α1-0) in FIG. 4, respectively.

Now, the horizontal synchronization frequency fH-91 [
If J,1, then its horizontal synchronization period T, = 910
．． IT, '(L: counting clock period), so the horizontal oscillation counter circuit 6 only needs to count 910.1 clocks. However, in reality, the horizontal oscillation counter circuit 6 can only count N clocks (N: natural number). Therefore, the above-mentioned fine adjustment is performed by the delay circuit 7, and its method is to change the counting clock frequency by shifting the phase of the counting clock by 0.1 clock every horizontal period, and as a result, the horizontal oscillation frequency can be changed. It becomes possible to change. This control method will be explained below.

At a certain time, the count value of the horizontal oscillation counter circuit B is determined, and the count clock of FIG.
In other words, if the M extension circuit 70 input is selected, the input horizontal synchronizing signal period is Tn = 910. Since it is IT3, the delay amount control circuit 8 selects the output 1bI of the unit delay buffer circuit 301 when moving to the next water synchronization period. This situation is the case at time H3 in FIG. 4 f&1.

Furthermore, when moving to the next horizontal synchronization period, the output f01 of the unit delay buffer circuit 602 is selected in the same way, and this
This is the case at time H7 in cIK.

Thereafter, it sequentially moves from IC1 to (dl, from ldl to (-)), and from (1) to U). Finally, when it moves to 01, it returns from Q) to (α) and repeats the above operation.In this example, the fine delay delay is 0.1 clock, but when it is 0.2 clock (Starting from α1, (α1 → fC1 → (e1 → ke) → +i+ → (51C as in α1) (.The above control is possible when the delay cover is 0.5 clocks or less, When the delay amount control circuit 8 is larger than that, the delay amount control circuit 8 switches the delay cover at a position delayed by one clock further than the switching timing in the above-mentioned control.This situation is shown in FIG. In a relationship such as synchronous period TH = 910.B T, the counting clock switches from (α) to lil in Fig. 4, but if it switches at the H80 position of &l in Fig. The clock shown on the i line of (L) becomes redundant.Therefore, from time H1, the counting clock 1
The output clock of the delay circuit 7 is stopped until time H, which is delayed by the clock cycle, and at time H5 lj
It operates to select l. This clock stop control @
The signal is generated by the delay control circuit 8 and
When applied to the l path 625, it operates to stop the output clock of the delay circuit 7.

By shifting the phase of the counting clock from the VCO 5 in FIG. 1 as described above, it is possible to finely adjust the low frequency of the horizontal synchronization oscillation. Next, details of the delay amount control circuit 8 described above will be explained. FIG. 5 is a Pronk diagram showing the details, in which 501 is a decoder circuit, 502 is a latch circuit,
506 is a switching circuit, 504 is a subtraction circuit, 505 is a comparison circuit, 506 is an addition circuit, 507 is a discrimination circuit that determines whether the delay control amount from the loop filter 10 is shorter than the 05 clock, and 508 is a yJ child. counter circuit,
5091EOR circuit, 510 and 511 are 9792170
There are 71 circuits. The control signal from the loop filter 10 is added to the delay amount selection data held in the latch circuit 502 one horizontal period (hereinafter abbreviated as 1H) before. At this time,
If the Zllll calculation power becomes larger than the data for selecting line 01 in FIG.
5 detects this and connects the switching circuit 506 to the reduction circuit 504. Subtraction circuit 5040 subtraction operation is performed by delay circuit 70
If the number of stages of the unit delay buffer circuit is N, and the number of excess stages when their total delay type exceeds one counting clock cycle is N, then (A'-rL) is the number of stages of the adder circuit 506. By subtracting from the output selection data (thereby, selection data for determining which M-length buffer circuit should be selected next is obtained. In the case of FIG. 6, N=9.7
Since L==Q, (7) is selected, that is,
When the mJ small output is 10, when a control signal is issued from the loop filter 10 to further delay the delay buffer circuit by two stages, the output of the subtraction circuit 504 becomes 2,
(A signal is generated to select 151. The control signal obtained in this way is latched every 1H by the latch circuit 502. This latch clock delays the output pulse of the horizontal output circuit 15 by the latch circuit 511. Use the pulse latched by the output clock of circuit 7. Furthermore, launch circuit 502
The output passes through a decoder circuit 501 and is applied to a delay circuit 7 to control the amount of delay. The above is when the delay control signal from the loop filter 10 is a delay control of 0.5 clocks or less, and when it is larger than 0.5 clocks, the above latch clock is further emitted from the latch circuit 510.
OR (exclusive OR) is performed in the EOR circuit 509, this clock is counted in the counter circuit 508, and a pulse is generated to stop the output clock of the delay circuit 7 by 1022 minutes of the clock. It is input to circuit 325. At this time, the discrimination circuit 507 uses the counter circuit 508
When the delay amount control signal of the loop filter 1o is delayed by 0.5 clocks or less, the counter circuit 508 is set to a set state, and the counting clock input to the AND circuit 325 is passed through as is. In this way, the delay amount control signal is generated.

FIG. 6 shown below shows another embodiment of the delay circuit 7. In FIG. 601 to 609 are buffer circuits with control terminals, which are so-called tristate buffers, and 610 to 609 are buffer circuits with control terminals.
617 is a buffer circuit for the delay element. These tri-state buffer 7 circuits 601 to 609 pass the input counting clock from the VCO 5 through buffer circuits 610 to 617 when a control signal is applied to each control terminal, and when no control signal is applied, the output is high. It becomes an impedance state.

Another embodiment of the above-mentioned delay amount control is shown in FIG. Here, 701 is a switching circuit, 702 is an 11 subtraction circuit, and the other parts have the same numbers as in FIGS. 3 and 5 and have the same functions.

In FIG. 5, the control equal signal from the loop filter 10 is 0.
When a delay larger than 5 clocks is required, the output clock of the delay circuit 7 is stopped for one clock period and then the delay amount is selected.In this embodiment, however, in such a case, the counter circuit The preset value given to −
1, and the counter circuit 60 count number is increased by 1. -Then, the delay circuit 7 selects one of the outputs of each unit delay buffer circuit shown in FIG. The selection method is performed in the same manner as in the case of delay control in which the control signal from the loop filter 10 is 0.5 clocks or less among the operations of the delay amount control circuit 8 shown in FIG. In other words, the explanation using the waveform diagram of FIG. 4 is as follows.

Now, if the output of delay circuit 7 has selected (α),
When there is a relationship of Tg = 91 o, a5, the following 1H
If the delay amount control circuit 8 issues a control signal so that the clock is delayed by 0.8 clocks in the period, then the clock is switched to +i+. At this time, as shown in (L), the clock changes at time H3, so a broken line clock appears, -〇,
It appears to be delayed by 2 clocks. However, at this time, the discrimination circuit 507 in FIG.
The count value has increased by 1 clock, so it's a click)
Ifil becomes 911, and as a result, the above-mentioned 10 and 2
In addition to the delay of 100 ms, it becomes possible to satisfy the relationship T5=910.87'.

As described above, according to this embodiment, by arranging the M extension circuit 7 before the horizontal oscillation circuit 6, the delay t of the delay circuit can be increased by 1x, (, horizontal synchronized reproduction with high accuracy is possible. becomes.

〔Effect of the invention〕

According to the present invention, by configuring the horizontal synchronization device for television reception with a digital circuit and delaying the counting clock by the operation of the delay circuit, it is easy to finely adjust the output phase and frequency of the horizontal oscillation counter circuit. Since the count directivity of the counter circuit does not change once synchronization is established, stable synchronization 4N-1 can be obtained, and the node configuration can be made with almost the same hardware configuration as before, so LSI etc. This has the effect that it can be fully incorporated into

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the horizontal synchronization regeneration circuit according to the present invention, FIG. 2 is a conceptual diagram illustrating the operation surrounded by the broken line B in FIG. 1, and FIG. 4 is a waveform diagram for explaining the delay operation in FIG. 3; FIG. 5 is a block diagram showing details of the delay amount control circuit in FIG. 3; 6 is a circuit diagram showing another embodiment of the delay circuit in FIG. 3, FIG. 7 is a block diagram showing details of another embodiment of the portion surrounded by the broken line B in FIG. 1, and FIG.
9 is a block diagram showing a conventional example, and FIG. 9 is a waveform diagram for explaining the operation of FIG. 8. 1...Al1) Converter 21...Burst extraction circuit 22...Phase detection circuit 3...Frequency division circuit 4...Bundle conversion circuit 5...VCO6...Horizontal counter circuit 7...・Delay circuit 8...Delay amount control circuit 9...Decoder 10...Loop filter
11... Synchronization separation circuit 12... Phase detection circuit
13...Integrator circuit agent Patent attorney Ogawa h Sake slip 1 figure closed 2 figures ts) 'II7・Usen8 figure 0S Bud 3 figure

Claims (1)

[Claims] 1. A clock generating means for generating a system clock that is phase-synchronized with a burst signal in a composite video signal, and a stable horizontal system that is synchronized with a horizontal synchronization signal included in the composite video signal using the clock. The horizontal synchronization reproduction means has a horizontal synchronization reproduction means for generating a synchronization reproduction signal, and the horizontal synchronization reproduction means includes a horizontal output circuit that drives the deflection system of the television receiver, and a 90 degree phase shifter that integrates or shifts the phase of the output of the output circuit. a synchronization separation circuit for separating horizontal and vertical synchronization signals from the composite video signal, a horizontal synchronization signal obtained by the separation circuit, and the above-mentioned 9.
A phase detection circuit that compares the phase of the signal obtained by the 0 degree phase shift circuit; an averaging circuit that averages the output signal of the phase detection circuit; a delay circuit that delays the system clock by a predetermined amount; a horizontal oscillation circuit that counts the system clock delayed by the delay circuit a predetermined number of times based on another output of the averaging circuit; 2. The horizontal synchronization reproducing circuit according to claim 1, further comprising a horizontal drive circuit for providing a signal to the circuit. 2. The clock generation means includes a burst extraction circuit that extracts a burst signal from the composite video signal, a voltage controlled oscillation circuit that generates a system clock, a frequency division circuit that divides the output clock of the oscillation circuit by a predetermined amount. It is characterized by comprising a phase detection circuit that compares the phase between the output of the frequency dividing circuit and the output of the burst extraction circuit, and an averaging circuit that averages the output of the detection circuit and generates a control voltage for the voltage controlled oscillation circuit. A horizontal synchronous reproducing circuit according to claim 1.