JPS6037824A - Pll circuit - Google Patents

Pll circuit

Info

Publication number
JPS6037824A
JPS6037824A JP58145537A JP14553783A JPS6037824A JP S6037824 A JPS6037824 A JP S6037824A JP 58145537 A JP58145537 A JP 58145537A JP 14553783 A JP14553783 A JP 14553783A JP S6037824 A JPS6037824 A JP S6037824A
Authority
JP
Japan
Prior art keywords
output
controlled oscillator
input signal
voltage controlled
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58145537A
Other languages
Japanese (ja)
Inventor
Yoshibumi Nakajima
Toshio Hashi
Kazuharu Chiba
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58145537A priority Critical patent/JPS6037824A/en
Publication of JPS6037824A publication Critical patent/JPS6037824A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0807Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal

Abstract

PURPOSE:To eliminate adverse effect to be exerted onto a post-stage circuit by turning off the output signal of a PLL circuit when no input signal is fed to a phase comparator. CONSTITUTION:The phase comparator 1 compares a 1/n frequency division signal of an input signal with a 1/m frequency division signal of a voltage controlled oscillator 3 in phase and outputs an error voltage l in response to the phase difference. This output voltage l is smoothed by a low pass filter 2 and goes to a control voltage (c) of the voltage controlled oscillator 3. As a result, an output frequency of the voltage controlled oscillator 3 is synchronized with the input signal frequency. When the input signal level to the PLL circuit is judged as normal by a level detector 6, an output switch 7 is turned on and the output of the voltage controlled oscillator is fed to the circuit of the next stage but when the result is judged as abnormal because the input signal level is zero or very low, the output switch 7 is turned off and no output of the voltage controlled oscillator 3 is transmitted to the next stage circuit.
JP58145537A 1983-08-09 1983-08-09 Pll circuit Pending JPS6037824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58145537A JPS6037824A (en) 1983-08-09 1983-08-09 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58145537A JPS6037824A (en) 1983-08-09 1983-08-09 Pll circuit

Publications (1)

Publication Number Publication Date
JPS6037824A true JPS6037824A (en) 1985-02-27

Family

ID=15387485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58145537A Pending JPS6037824A (en) 1983-08-09 1983-08-09 Pll circuit

Country Status (1)

Country Link
JP (1) JPS6037824A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2652698A1 (en) * 1989-10-02 1991-04-05 Sgs Thomson Microelectronics DECODER FOR DECODING A CRYPT SOUND.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2652698A1 (en) * 1989-10-02 1991-04-05 Sgs Thomson Microelectronics DECODER FOR DECODING A CRYPT SOUND.
EP0424201A1 (en) * 1989-10-02 1991-04-24 STMicroelectronics S.A. Decoder for decoding an encrypted television audio signal

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