JPS62285519A - Apll no input signal compensation circuit - Google Patents

Abstract

PURPOSE:To attain immediate lock-in when an input signal is intermitted and a data is restored again by providing a specific circuit holding the state of a point of time when the last data is inputted. CONSTITUTION:In the APLL circuit comprising a phase comparator 1, a voltage controlled oscillator 5 connected to an output of the comparator 1, and a feedback path connecting the output of the voltage controlled oscillator 5 and the one input of the phase comparator, an integration means 2 integrating the output of the phase comparator 1, an input signal detection circuit 4 detecting the presence of an input signal to the phase comparator 1, a switch 6 controlled by the input signal detection circuit 4 and a hold means 3 holding two outputs of the integration means while being connected to the output of the integration means 2 via the switch 6 are provided between the phase comparator 1 and the voltage controlled oscillator 5. Thus, when the input signal is interrupted and then restored again, the immediate lock-in is attained.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Technical Field of the Invention] The present invention is based on APLL (Analog PLL)
This article relates to the APLL no-signal compensation circuit, and is particularly concerned with the APLL no-signal compensation circuit, which is designed to stabilize when there is no signal.

[Technical Background of the Invention] Conventionally, an APLL circuit as shown in FIG. 3 has been used in a standard manner. This consists of a phase comparator l, a voltage controlled oscillator 2, and a feedback path 3. To show the connection relationship, the phase comparator 1 is connected to the voltage controlled oscillator 2 via the integrator 4, and the voltage controlled oscillator 2 is connected to the phase comparator l via the feedback path 3. The integrator 4 is composed of an operational amplifier, a capacitor, and a resistor.

[Problems with the Background Art] However, in this circuit, the state of the APLL circuit is not maintained when the input signal is interrupted, so even after the input signal returns to normal, the a-tuck-in time becomes longer and lock-in occurs. There were some problems, such as in some cases not being possible. What is shown at tl in FIG. 3 is the operation when the circuit is activated, and the rise time is considerably longer than during normal operation. Obviously, it is not possible to demodulate the data until lock-in occurs. Therefore, this causes a decrease in efficiency during the entire communication period. Furthermore, if the input signal is interrupted, the phase comparison operation continues, causing the voltage controlled oscillator to shift to a breaking point.

As a result, the phase difference between the input signal and the output signal may exceed a certain lock-in range, and even after the input signal returns to normal, there is a possibility that normal data demodulation may not be possible.

[Object of the Invention] The present invention was made in order to eliminate the drawbacks of the conventional circuit as described above, and provides an APLL no-signal compensation circuit that can immediately lock in when the input signal is interrupted and then restored. It is intended to.

[Summary of the Invention] In order to achieve the above object, an APLL no-signal compensation circuit according to the present invention includes a phase comparator, a voltage-controlled oscillator connected to the output of the phase comparator, and a voltage-controlled oscillator connected to the output of the voltage-controlled oscillator. In an APLL circuit comprising an output and a feedback path connecting one input of the phase comparator, an integrating means for integrating the output of the phase comparator between the phase comparator and the voltage controlled oscillator; an input signal detection circuit for detecting the presence or absence of an input signal to the phase comparator; a switch controlled by the input signal detection circuit; and an output signal connected to the output of the integration means via the switch; and a holding means for holding the.

[Embodiments of the Invention] Preferred embodiments of the present invention will be described below with reference to FIG. In this embodiment, the APLL no-signal compensation circuit of the present invention is composed of a phase comparator 1, an integrator 2, a feedback path 3, a voltage hold circuit 3 as a holding means, an input signal detection circuit 4, a voltage controlled oscillator 5, and a switch 6. be done. To show the connection relationship, the phase comparator 1 is connected to the integrator 2, and the integrator 2 is connected to the switch 6.
The voltage hold circuit 3 connects to the voltage control oscillator 5, the voltage control oscillator 5 connects to the phase comparator l via the feedback path 3, and the input signal detection circuit 4 receives the input signal a.
are connected to each. Note that the switch 6 is controlled by the input signal detection circuit 4.

The phase comparator 1 is composed of an operational amplifier, and the integrator 2 is composed of an operational amplifier, a capacitor, and a resistor. The voltage hold circuit 3 is composed of an operational amplifier and an input stage capacitor.

Next, the operation of this embodiment will be explained. The phase comparator 1 compares the phases of two input signals and outputs a signal with a voltage □ proportional to the phase difference. The integrator 2 receives the output of the phase comparator i, operates as a filter, and outputs a voltage corresponding to the direction and amount to be converged.

The input signal detection circuit 4 detects the presence or absence of an input signal, turns on the switch 6 if there is an input signal, and turns it off if the input signal is interrupted.

(1) First, when there is an input signal, the output of the integrator 2 is transmitted to the voltage hold circuit 3 via the switch 6. At this time, circuit constants are selected so that the voltage hold circuit 3 is sufficiently driven by the output of the integrator 2. Therefore, in this case, a signal is transmitted.

The voltage hold circuit '#i3 controls the voltage controlled oscillator 5,
It fires at the corresponding frequency and supplies the signal to the phase comparator 1.

(2) Next, when the input signal is interrupted, the switch 6 is turned OFF by the input signal detection port yi4 as described above, so the input terminal voltage of the voltage hold circuit 3 at the time when the last input signal was received is retained.

Let us assume that the input signal is interrupted and the input signal is input again. Since the last voltage is held in the voltage hold circuit Pi3, when the input signal is input again, the phase difference between the two inputs of the phase comparator l is relatively small. This results in lock-in in a very short period of time.

FIG. 2 shows the timing when performing 1N data adjustment using the PLL circuit shown in FIG. During data demodulation, input signal a, PLL control voltage S, PLL control vs.
! The pressure hold C and the data demodulated signal d operate as shown in the figure. In input signal a, tl-t2, t3-t4
, t5- is a period during which data is being received.

[Effects of the Invention] As is clear from the above embodiments, the APL according to the present invention
The L no-signal compensation circuit has a circuit that maintains the barking state at the time when the last data was input when the input signal is interrupted.
Immediate lock-in is now possible when the data is restored.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the APLL no-signal compensation circuit according to the present invention, No. 21! I is a timing chart showing the operation of the same embodiment, and FIG. 3 is a block diagram showing an example of the configuration of a conventional PLL circuit. 1008 phase comparator 280. Integrator 310. Voltage hold circuit (holding means) 4191 input signal input circuit 540. Voltage controlled oscillator 6...switch 751. Return Route Agent Patent Attorney Moritani-O Figure 2

Claims (1)

[Claims] APL consisting of a phase comparator, a voltage controlled oscillator connected to the output of the phase comparator, and a feedback path connecting the output of the voltage controlled oscillator and one input of the phase comparator.
In the L circuit, integrating means for integrating the output of the phase comparator between the phase comparator and the voltage controlled oscillator;
an input signal detection circuit for detecting the presence or absence of an input signal to the phase comparator; a switch controlled by the input signal detection circuit; and an output signal connected to the output of the integration means via the switch; 1. An APLL no-signal compensation circuit comprising: a holding means for holding;