JPH06244715A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a phase synchronizing circuit in which a normal and stable synchronizing state can be held regardless of the influence of a noise. CONSTITUTION:The phase synchronizing circuit is equipped with a voltage control oscillator 11, first subtracter 12, second subtracter 13, switch 14, threshold value discriminator 15, and noise discriminator 16. The voltage control oscillator 11 varies the frequency of an oscillation signal by an input control voltage. The first subtracter 12 searches a difference between an input timing signal and the oscillation signal, and outputs it. The switch 14 sets a signal to be inputted to the second subtracter 13 to an output signal from a ground potential or the first subtracter 12. The threshold value discriminator 15 switches the switch 14 based on the output signal from the first subtracter 12. The second subtracter 13 outputs a result obtained by comparing the input signal set by the switch 14 with a reference voltage Vref as the control voltage. The noise discriminator 16 controls the operation of the threshold value discriminator 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit applicable to the field of communication technology, and more particularly to a phase locked loop circuit usable for establishing a stable sync signal in an analog sync circuit.

[0002]

2. Description of the Related Art Conventionally, a phase locked loop is often used in the field of communication technology. To guarantee the synchronization in this phase locked loop, a method of supporting the sync loop from the periphery by using code logic such as error correction and a bandpass filter has been used.

In some cases, in order to guarantee synchronization, the input voltage of the voltage controlled oscillator is fixed for a certain period of time when noise is generated, abnormal oscillation due to a noise signal is prevented, and the synchronization state is temporarily maintained within the synchronization guarantee. The method of keeping was also considered.

[0004]

The above-mentioned conventional phase locked loop circuit has a drawback that it is out of sync due to the influence of noise and cannot maintain a normal and stable sync state.

Also, in the method of fixing the input voltage of the voltage controlled oscillator for a fixed time, since the fixed time is obtained by the timer, the input voltage cannot be fixed for all the time when noise is generated. There were also drawbacks.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a phase locked loop circuit capable of maintaining a normal and stable sync state regardless of the influence of noise.

In order to achieve the above-mentioned object, the phase locked loop circuit of the present invention comprises a voltage controlled oscillator that varies the frequency of an oscillation signal according to an input control voltage and a difference between an input timing signal and an oscillation signal. In the phase locked loop circuit including one subtractor and a second subtractor that takes the difference between the difference signal from the first subtractor 12 and the reference voltage and outputs it as a control voltage, Switching means for taking the output signal and setting the input signal of the second subtractor to the ground potential or the output signal from the first subtractor, a signal obtained by squaring the input timing signal, and after delaying the input timing signal A noise determiner for adding the squared signals and controlling the operation of the switching means based on the addition result is provided.

Here, the switching means takes in a switch for setting the input signal of the second subtractor to the ground potential or the output signal from the first subtractor and the output signal from the first subtractor. It may be composed of a threshold value judging device which switches and controls a switch based on a signal.

As described above, in the present invention, when noise is generated, it is judged by the noise judging device to make the switching means operable, and the switching device makes the input of the second subtractor a ground potential to control the voltage. Fix the oscillation frequency of the oscillator. As a result, a constant frequency is output from the output terminal.

When the noise disappears, it is judged by the noise judging device and the switching means is operated to supply the output signal from the first subtracting device to the input of the second subtracting device. .

Therefore, regardless of the length of the noise, it is possible to largely guarantee the synchronization.

[0012]

The present invention will now be described with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the phase locked loop circuit of the present invention. The phase locked loop circuit shown in FIG. 1 includes a voltage controlled oscillator 11, a first subtractor 12, and a second subtractor 1.
3, a switch 14, a threshold value judging device 15, and a noise judging device 16.

Here, the input terminal T _i is the first subtractor 1
2 is connected to the inverting input terminal and the noise determiner 16, and the input timing signal R is the first subtractor 12
Is supplied to the inverting input terminal and the noise determiner 16. The first subtractor 12 takes the difference between the oscillation signal from the voltage controlled oscillator 11 and the input timing signal R, and outputs the difference signal to one fixed contact a of the switch 14 and the threshold value judging device 1.
Enter 5 and. The other fixed contact b of this switch 14
Is connected to the ground potential GND and the moving contact is connected to the non-inverting input terminal of the second subtractor 13. The threshold determiner 15 switches the switch 14 based on the difference signal.
Is switched to one fixed contact a or the other fixed contact b. The offset voltage V _ref is supplied to the inverting input terminal of the second subtractor 13, and the second subtractor 13 compares the offset voltage V _ref with the signal from the moving contact of the switch 14. The output terminal of the second subtractor 13 is connected to the control terminal of the voltage controlled oscillator 11, and the voltage controlled oscillator 11 oscillates the oscillation output signal r according to the output voltage from the second subtractor 13. The voltage controlled oscillator 11 is connected to the output terminal T ₀ and
It is connected to the non-inverting terminal of the first subtractor 12. Further, the noise determiner 16 is adapted to form a reset signal for returning the threshold determiner 15 to the initial state based on the input timing signal R.

FIG. 2 is a block diagram showing an example of the configuration of the noise determiner of the phase locked loop.

The noise determiner 16 includes a first multiplier 21 and
π / 2 delay device 22, second multiplier 23, and adder 24
And a threshold value judging device 25. That is,
The input timing signal R is the first multiplier 21 and π /
It is adapted to be applied to the 2-delay device 22. The first multiplier 21 squares the input timing signal R and outputs the calculation result to the adder 24. Also,
The input timing signal R is delayed by π / 2 by the π / 2 delay device 22 and supplied to the second multiplier 23. The adder 24 can add the output signal from the first multiplier 21 and the output signal from the second multiplier 23. The output from the adder 24 is supplied to the threshold value determining device 25. The threshold value determiner 25 can supply the threshold value determination result to the threshold value determiner 15 as a reset signal.

The operation of the embodiment having such a configuration will be described.

The voltage controlled oscillator 11 includes a second subtractor 13
It oscillates with the output voltage from, and the oscillation output signal is output from the terminal T ₀ and is input to the non-inverting input terminal of the first subtractor 12. The first subtractor 12 outputs the input timing signal R so that the output result becomes zero.
And the oscillation output signal r match, the comparison result is output. The output signal of this comparison result is normally the switch 14
Since it is supplied to the second subtractor 13 through the contact a of
The voltage controlled oscillator 11 oscillates so that the oscillation output signal r of the voltage controlled oscillator 11 matches the input timing signal R.

During this period, if noise enters the input timing signal R, a large difference appears in the output of the first subtractor 12, causing the voltage controlled oscillator 11 to abnormally oscillate and out of synchronization. At this time, the threshold value determiner 15 detects this loss of synchronization from the output of the first subtractor 12, and immediately sets the input voltage of the voltage controlled oscillator 11 to the offset voltage V.
_Since only _ref is used, the switch 14, which has been on the fixed contact b side until now, is switched to the fixed contact a side. At this time, since the output of the noise judging device 16 outputs the reset signal before the noise is generated, the threshold judging device 15 operates the switch 14
Is fixed to the fixed contact b side, but after noise is generated, an active signal is output, and the switch 14 is set to the threshold judgment unit 1.
It is left to the output of 5. Thus, even if there is noise intrusion, the loss of synchronization can be detected within the guarantee of synchronization, and the oscillation frequency of the voltage-controlled oscillator 11 can be fixed during the period in which noise is occurring, thereby preventing loss of synchronization. The return of the switch 14 to the fixed contact b side due to the disappearance of noise becomes a normal state when the output of the noise determiner 16 becomes a reset signal output.

Next, the operation of the noise determiner 16 will be described. The input timing signal R is the first multiplier 21.
Squared in. The input timing signal R is π / 2.
After being delayed by π / 2 in the delay device 22, the second multiplier 23 squares the signal. Next, the output signals from the first multiplier 21 and the second multiplier 23 are added by the adder 24, and then the added signal is supplied to the threshold value determining unit 25. The threshold value determiner 25 determines that the addition signal is less than or equal to "1" or greater than "1".

Describing this with a mathematical expression, assuming that the input timing signal R is R = Sin θ, the noise is N, and the noise detection signal is V, the noise judging device 16 realizes the following mathematical expression. Will be. That is,

[0022]

## EQU1 ## V = (Sin θ + N) ² + {Sin (θ + π / 2)} ² = Sin ² θ + Cos ² θ + N ² + 2NSin θ = 1 + N ² + 2NSin θ (1)

From the above equation (1), the noise detection signal V
It can be seen that for N = 0, V = 1 and for N ≠ 0, V> 1.

As a result, the threshold value judging device 25 of the noise judging device 16 can output the presence or absence of noise when V is "1" or more.

As described above, in this embodiment, the output signal of the first subtractor 12 is threshold-value judged by the threshold-value judging device 15, and its output is held for the time when noise is generated, By inputting the ground potential to the one subtractor 12, the oscillation frequency of the voltage controlled oscillator 11 is fixed for an appropriate time. Therefore, the conventional code logic for error correction or the like, the bandpass filter, or the like is provided around the synchronizing circuit. Unlike the method supported by the above, since a circuit for performing synchronization guarantee can be provided directly in the loop portion of the synchronization circuit, it is possible to provide a large amount of synchronization guarantee accurately.

[0026]

As described above, according to the present invention, the difference between the input timing signal and the synchronizing signal is threshold-determined,
By holding the output for the time when noise is generated and fixing the oscillation frequency of the voltage-controlled oscillator only for the time when noise is generated, it is possible to ensure accurate synchronization and to have a large guarantee. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit of the present invention.

FIG. 2 is a block diagram showing a configuration example of a noise determiner used in the same embodiment.

[Description of Reference Signs] 11 voltage controlled oscillator 12 first subtractor 13 second subtractor 14 switch 15, 25 threshold value determiner 16 noise determiner 21 first multiplier 22 π / 2 delayer 23 second Multiplier 24 Adder

Claims (2)

[Claims] 1. A voltage-controlled oscillator that varies the frequency of an oscillation signal according to an input control voltage, a first subtractor that takes a difference between an input timing signal and the oscillation signal, and a first subtractor 12 In a phase-locked circuit having a second subtractor that takes the difference between the difference signal and the reference voltage and outputs the difference as a control voltage, the output signal from the first subtractor is taken in, and the second subtractor Switching means for setting the input signal to the ground potential or the output signal from the first subtractor, a signal obtained by squaring the input timing signal, and adding the signal squared after delaying the input timing signal,
And a noise determiner for controlling the operation of the switching means based on the addition result. 2. The switch means sets a switch for setting an input signal of the second subtractor to a ground potential or an output signal from the first subtractor, and takes in an output signal from the first subtractor. 2. The phase locked loop circuit according to claim 1, further comprising a threshold value judging device for switching and controlling the switch based on this signal.