JPH04307816A - Phase synchronization circuit - Google Patents

Abstract

PURPOSE:To establish stable synchronization state by simply and surely preventing out of synchronism due to effect of input noise in the phase synchronization circuit. CONSTITUTION:A level of an output 5 of a subtractor 4 representing a phase difference between an input signal 1 and an oscillation output 3 of a VCO 2 is detected by a threshold discrimination section 9. When a fault takes place in the input signal 1 and a level of a phase difference detection output 5 exceeds a prescribed threshold range, a hold section 10 with a timer selects a switch 6 for a prescribed time to fix an input of a 2nd subtractor 7 to a ground potential. Then a control voltage 8 of the VCO 2 is constant for the period and a frequency of the oscillation output 3 is made constant to keep the synchronization state.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked circuit, and more particularly to an analog phase-locked circuit.

0002

[Prior Art] As a method for assuring synchronization in an analog phase-locked circuit that establishes phase synchronization of analog signals, there is no particular hardware added to the phase-locked loop to directly guarantee synchronization, and code logic such as error correction, etc. The current situation is to rely on a method of supporting the synchronous circuit from the periphery using a bandpass filter.

[0003] Therefore, the conventional phase synchronization circuit has the drawback that it is unable to maintain a normal and stable synchronization state because it loses synchronization due to the influence of large noises.

0004

[Object of the Invention] Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and its purpose is to achieve a stable synchronization state without losing synchronization due to the influence of large noise. The objective is to provide a phase-locked circuit that can guarantee the following.

[0005]

According to the present invention, there is provided a voltage-controlled oscillation means whose oscillation frequency is controlled according to a control voltage, a phase difference between the oscillation output and an input signal, and detection according to the phase difference. A phase-locked circuit comprising means for generating a signal and means for generating the control voltage in response to the detection signal, the control voltage being set to a constant value when the level of the detection signal exceeds a predetermined range. A phase-locked circuit characterized in that it includes clamping means is obtained.

[0006]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an analog synchronous circuit according to an embodiment of the present invention. The input signal 1 is subtracted from the oscillation output 3 of the voltage controlled oscillator (VCO) 2 in a subtracter 4, thereby generating a detection signal 5 according to the phase difference between the two signals.

This detection signal 5 is passed through a switch 6 to a second
This is one input of the subtracter 7, and a reference voltage is applied to the other inputs. Therefore, a difference signal 8 between the detection signal 5 and the reference voltage is obtained by the subtracter 7, and this difference signal 8 is used as a control voltage for the VCO 2.

The detection signal 5, which is the output of the subtractor 4, is also input to a threshold determination section 9, and the threshold determination section 9 determines whether the level of the detection signal 5 is within a certain threshold range. It will be determined whether there is

This determination result is held for a certain period of time by a timer-equipped hold section 10 and becomes a control signal for the switch 6. Incidentally, after this certain period of time has elapsed, a reset signal 11 is generated to reset the threshold determination section 9 and return to the initial state.

In such a configuration, during normal operation (when synchronization is established), the threshold value determination section 9 does not detect any abnormality in the detection signal 5, so the output of the hold section 10 is connected to the switch 6.
A control signal is generated to maintain the state shown in the figure.

Therefore, the output 8 of the second subtractor 7 is the difference between the detection signal 5 and the reference voltage, which is used as the control voltage of the VCO 2, and the synchronous loop is in a synchronous state.

[0013] When large noise is superimposed on input signal 1,
The level of the detection signal 5 becomes high and exceeds the upper and lower thresholds of the threshold value determination section 9. As a result, a determination signal indicating an abnormality is output from the threshold value determination section 9, and the timer-equipped hold section 10 outputs a control signal for switching the switch 6 while holding the determination signal for a certain period of time.

Since the switch 6 is switched from the state shown in the figure to ground potential, the output 8 of the subtracter 7 will be clamped to a control voltage at a constant level. That is, since the output 8 is fixed to the reference voltage value (offset value) which is the other input of the subtracter 7, the VCO 2 oscillates at a constant frequency within the guarantee of synchronization, and loss of synchronization is prevented.

[0015] After a certain period of time has elapsed, it can be assumed that the influence of noise has disappeared, so the threshold value determination section 9 is reset by the reset signal 11 to return to the initial state.

[0016] In the above, an analog type phase synchronized circuit has been described, but it is clear that the present invention can be similarly applied to a digital type phase synchronized circuit.

[0017]

[Effects of the Invention] As described above, according to the present invention, an abnormality in the signal level indicating a phase difference is detected and the control voltage of the VCO is adjusted.
Since the voltage is fixed to a constant frequency within the range of guaranteeing synchronization, it is possible to guarantee synchronization very easily and reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.

[Explanation of symbols]

2 VCO 4,7 Subtractor 6 Switch 9 Threshold determination section 10 Hold part with timer

Claims (1)

[Claims] 1. Voltage-controlled oscillation means whose oscillation frequency is controlled according to a control voltage, and means for detecting a phase difference between the oscillation output and an input signal and generating a detection signal according to this phase difference. , means for generating the control voltage in response to the detection signal, and means for clamping the control voltage to a constant value when the level of the detection signal exceeds a predetermined range. A phase-locked circuit characterized by: