JPS6036908Y2 - Phase comparator with automatic phase control method - Google Patents

Description

[Detailed description of the invention] This invention is a phase-locked loop (PLL) with automatic phase control system.
The present invention relates to a phase comparator constituting a phase comparator, and particularly relates to an automatic phase control type phase comparator that can stably oscillate a voltage controlled oscillator without fluctuation even when a reference frequency is missing.

Generally, a phase comparator 1 in an automatic phase control (APC) type oscillator as shown in FIG. It works to output an error voltage according to the
A method such as that disclosed in Japanese Patent No. 42661 has been used.

That is, to explain this based on FIG. 2, the output fo of the voltage controlled oscillator 2 and the output fr of the reference frequency 3 are passed through waveform shaping circuits 4 and 5, respectively, and shaped as shown in FIGS. 3A and B. After that, the overlapping time of both outputs is detected by the NAND gate 6, and this output C is used to control the transistor 7 and charge of the capacitor 8, so that the oscillation frequency fo of the voltage controlled oscillator 2 becomes an integer of the reference frequency fr. The control is performed so that the number increases by N times.

In this method, in the locked state, the charge in the capacitor 8 is discharged through the resistor 9, so it is charged every time it is sampled, and the oscillation frequency is controlled to be constant over a long period of time. However, when looking at a short period of time, it cannot be said that there is sufficient stability during discharge.

Furthermore, in this case, if the reference frequency is missing, the phase comparison is stopped, so that the capacitor 8 further discharges, the potential decreases, and the oscillation frequency of the voltage controlled oscillator 2 fluctuates.

Therefore, the present invention was developed in view of the above points, and charges and discharges during sampling comparison, holds the charge of the capacitor constant during other periods, and also maintains the charge of the capacitor constant even when the reference frequency is missing. To provide a phase comparator that can maintain and obtain a stable oscillation frequency fo.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 4, reference numeral 10 denotes a monostable multivalve generator that shapes the waveform of the output of the reference frequency oscillator 3; an OR gate that detects a match;
AND gates 13 and 14 are P-channel and N-channel FEs that are connected in series and constitute a charging/discharging control gate that controls charging and discharging of the capacitor 16 of the low-pass filter 15.
T is connected to be controlled by the outputs of the OR gate 11 and AND gate 12.

Then, the charging voltage of the capacitor 16 is determined by the voltage controlled oscillator 2.
is applied to

Next, the present invention having such a configuration will be explained based on the operational waveform diagrams of FIGS. 5 to 7.

First, when the oscillation frequency fo of the voltage controlled oscillator 2 is synchronized with the reference frequency, first, as shown in FIG.
Even if the capacitor 16 is discharged by turning ON, the P-channel FET 13 is then activated by the OR gate 11 output.
Since the capacitor 16 is charged with electric charge due to the conduction of remains unchanged.

However, as shown in FIG. 6, when the phase of the voltage controlled oscillator 2 lags, the output of the OR gate 11 and the AND gate
The pulse widths of the outputs become different, and the output width of the OR gate 11 becomes larger, so the amount of charge increases by the difference, the potential of the capacitor 16 rises, and it operates to increase the voltage-controlled oscillation frequency.

Conversely, if the oscillation frequency of voltage controlled oscillator 2 advances, AN
The output of the D gate 12 becomes larger than the output of the OR gate 11, and discharge is performed by the difference, lowering the potential of the capacitor 16 and acting to lower the oscillation frequency fo of the voltage controlled oscillator 2 (see Figure 7). ).

In addition, in the synchronized state, FETs 13 and 14 are in a non-conducting state except when phase comparison is being performed, and the charge in the capacitor 16 is not discharged, so that a stable frequency is always oscillated. Can be done.

Next, when the reference frequency is missing, fr becomes low level, fr becomes bilevel, and both FETs 13 and 14 are turned off.
F[, so that the charge in the capacitor 16 is prevented from being discharged.

In this way, even if the reference frequency is missing, the potential of the capacitor 16 is held constant, so the oscillation frequency of the voltage controlled oscillator 2 does not fluctuate.

Also, in the above explanation, the inverted output of the reference frequency was used, but
As shown in FIG. 8, an inverted output of the oscillation frequency of the voltage controlled oscillator 2 is created, and the reference frequency fr and the AND gate 17 are connected to the NAN
It is also possible to perform sampling comparison using the D gate 18.

As mentioned above, the phase comparator of the present invention detects the phase of the output of the reference frequency and the oscillation frequency of the voltage controlled oscillator using two matching gate circuits, controls the charge/discharge gate depending on the pulse width of the waist detection output, and This controls the charging and discharging of the capacitor of the filter, so that the capacitor load is not discharged except during charging and purchasing, and the charging and discharging control gate is turned OFF even when the reference frequency is missing, and voltage control is maintained. This prevents fluctuations in the oscillation frequency of the oscillator, and is useful in cases where data is transmitted without a reference frequency, such as in facsimiles, which transmit data using binary signals.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of APC, Figure 2 is a diagram showing a conventional example of a phase comparator, Figure 3 is a waveform diagram of the main part of Figure 2, and Figure 4 is the automatic phase control of the present invention. FIG. 5, FIG. 6, and FIG. 7 are diagrams showing the operating waveform diagram of FIG. 4, and FIG. 8 is a diagram showing another embodiment of the present invention. 1... Phase comparator, 2... Voltage controlled oscillator, 3... Reference frequency oscillator, 10...
・・Monostable multi-valve regulator-0

Claims (1)

[Scope of utility model registration request] It consists of a voltage controlled oscillator, a reference frequency oscillator, a phase comparator that detects the phase difference between the outputs of both optical oscillators, and a low-pass filter that converts the output of the comparator into a control voltage for the voltage controlled oscillator. In the automatic phase control method, the phase comparator outputs one of the voltage controlled oscillator and the reference frequency oscillator as a positive phase output and a negative phase output, and detects a match with the output of the other. and charging/discharging control gate means for controlling charging/discharging of the low-pass filter according to the output difference of the detection means, so that when the reference frequency signal is missing, the reference frequency signal is continuously maintained. Since the level is constant, the detection means does not detect a match, and the charge/discharge control gate means is cut off by the output of the detection means in such a state. Automatic phase control type phase comparator.