JPH0865156A - Phase locked oscillator - Google Patents

Abstract

PURPOSE: To improve the followup characteristic of the oscillator by extending the range of phase difference recognized normally by a phase comparator in a phase locked oscillator extracting a clock signal from received data. CONSTITUTION: An Up signal is set till a clock signal CLK reaches +π from a time when an edge of a reception signal Data is detected, and a Down signal is set till the signal CLK reaches +πfrom a time 0. When the edge of the detected signal Data and the position of the signal CLK are arranged, the Up/ Down signals are set simultaneously and kept for the same period. When the edge position detected from the reception signal Data is earlier than the phase of the signal CLK, the Up signal is set early and kept for a longer time than the Down signal. Conversely when the edge position is delayed more than the phase of the signal CLK, the Up signal is set with a delay. That is, the Up/ Down signals are operated by using a charge current source 2a and a discharge current source 2b of a charge pump 2 and the generated current is stored in a capacitor 2c as a charge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillator for extracting a clock from received data in bit timing (symbol timing) reproduction in digital communication, for example.

[0002]

2. Description of the Related Art Generally, PLL (Ph
An as-Locked Loop (phase-locked loop) circuit is used.

In digital communication, if there is a bit string (consecutive of the same symbol) in which a received signal does not change,
Since no edge is extracted from the received signal, a bit (symbol) cycle in which phase comparison is not possible occurs.

A PLL used for extracting a received clock in digital communication in which such phase comparison occurs intermittently.
As a circuit, a method in which a charge pump is activated only in a period in which phase comparison is performed, a circuit using a sample holder for removing a pulsating current voltage due to up / down charge generated at that time, and the like have been proposed.

FIG. 8 is a block diagram showing an example of the configuration of such a conventional PLL circuit, and FIG. 9 is an operation timing chart thereof.

This PLL circuit has a clock signal CLK output from a voltage controlled oscillator (VCO) 105 described later.
Comparator 10 for performing a phase comparison between the received signal Data and the received signal Data
One. The phase comparator 101 uses the rising edge position of the clock signal CLK as a reference for the received signal Dat.
The rising edge position of a is detected, and the Up / Down signal for controlling the charge pump 102 is output according to the result.

Here, as shown in FIG. 9, the Up signal is
The waveform rises at the rising edge of the reception signal Data and falls at the rising edge of the clock signal CLK.
The n signal has a waveform that rises at the falling edge of the Up signal and falls at the falling edge of the clock signal CLK. Then, the cycle in which the phase comparison is not performed (time t1, t2 in FIG. 9)
Up), the Up / Down signal is not generated in a period centered on.

The charge pump 102 has the above-mentioned Up / Do.
Charging current source 102a controlled by wn signal
And the discharge current source 102b, these current sources 1022a,
It is composed of a capacitor 103c for accumulating the current i generated in 102b as an electric charge, and is activated only for the period in which the phase comparison is performed.

A voltage v is generated in the capacitor 103c by the up / down charge of the charge pump 102. Since a pulsating current voltage is generated in this voltage v every time the phase comparison is performed (see the voltage waveform v in FIG. 9), the sample holder 103 is used to remove this.
Hold and sample the voltage after charge / discharge of the charge pump 102 by the Samp signal from the phase comparator 101 and hold it (see voltage waveform v ′ in FIG. 9).

After that, the output voltage v'of the sample holder 103 passes through the filter 104 and is input as the control voltage of the VCO 105.

[0011]

However, a phase comparator of the type in which the charge pump is activated only for the period in which the phase comparison is performed (hereinafter referred to as the first phase comparator. For example, I
In the above-mentioned conventional PLL circuit using the BM type), as shown in FIG.
As is clear from the above, a deviation of π / 2 constantly occurs between the rising edge position of the reception signal Data and the rising edge position of the clock signal CLK. As a result, the range of the phase difference in which the phase comparator 101 can normally operate can only secure ± π / 2 around the rising edge of the clock signal CLK, which causes a problem that an accurate phase comparison cannot be performed. there were.

Further, in this type of PLL circuit, since the discharge current is generated subsequent to the charge current, a triangular wave pulsating voltage is generated in the cycle in which the phase comparison is performed as described above (see FIG. 9). See voltage waveform v). on the other hand,
Since this pulsating current voltage is not generated in the cycle in which the phase comparison is not performed, the average voltage of the control signal to the VCO 105 is deviated between the cycle in which the phase comparison is performed and the cycle in which the phase comparison is not performed. Stability will be lost.

Therefore, in order to remove this pulsating voltage,
As described above, the sample holder 10 as shown in FIG.
A PLL circuit using 3 has been proposed. However, in this PLL circuit, the voltage v of the charge pump 102 after phase comparison is determined at the time point of + π from the rising edge of the clock signal CLK (see FIG. 9: time point of the falling edge of the Down signal). The average time until the result of the comparison is taken into the sample holder 102 and reflected in the voltage v ′ is about 3 from the rising edge position of the received signal Data.
It takes π / 2, which is a factor that delays the tracking characteristic of the PLL circuit.

As described above, since various problems occur when the first phase comparator is used, the edge position of the received signal Data and the clock generated by the VCO are used instead of the first phase comparator. The steady phase difference with the signal CLK can be set to 0 (the above-mentioned shift of π / 2 does not occur), and the charge / discharge completion time of the charge pump can be shortened (hereinafter referred to as the second comparator).
Called a phase comparator. For example, it is possible to use a Motorola type).

However, in this method, the charge pump is activated even in the period in which the phase comparison is not performed, so that there is a problem that abnormal voltage fluctuation occurs in this period and the PLL circuit malfunctions. Therefore, it is still the second
It was not possible to realize a PLL circuit using the phase comparator of (1), and it was still impossible to solve the above-mentioned problems such as slow tracking characteristics of the PLL circuit.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a phase-locked oscillator capable of expanding the range of the phase difference which can be normally recognized by the phase comparator. Is to provide. Another object is to provide a phase-locked oscillator in which an unnecessary pulsating flow component is not generated in the voltage of the charge pump that controls the VCO. Another object of the present invention is to provide a phase-locked oscillator capable of preventing malfunction by preventing abnormal voltage fluctuation due to the charge pump even in a cycle in which phase comparison is not performed. Still another object is to provide a phase locked oscillator with improved tracking characteristics.

[0017]

In order to achieve the above object, a feature of the present invention is to provide a phase comparison means for performing phase comparison between the clock signal and the input data at every constant cycle with reference to the clock signal. Charge pump means having a charging current source and a discharging current source that operate based on the phase comparison result of the phase comparison means, and a capacitor that stores electric charge according to the output of these current sources, and a voltage generated by the capacitor A sample holder for performing a sample-hold operation for holding, and a switch means for turning on at a period when the phase comparison by the phase comparison means is not performed, and feeding back the holding voltage of the sample holder to the capacitor of the charge pump, Filter means for limiting a frequency band with respect to a change in the holding voltage of the sample and hold means; Based on the output voltage of the filter means in that a voltage controlled oscillator whose oscillation frequency is controlled to output the clock signal.

The phase comparison means detects the edge of the input data and outputs an up signal which is set at the time of detection and is cleared at + π of the cycle of the clock signal, and the clock signal. Both the down signal and the up signal output over the period of 0 to + π in the same manner as
Sampling instructing means for detecting that all the signals have been output during a period of π and outputting a meet signal, and set signal generating means for outputting a set signal when the meet signal is not set at time + π of the clock signal. The charge current source and the discharge current source of the charge pump means operate based on the up signal and the down signal, respectively, and the sample holder performs the sample hold operation based on the meet signal. It is preferable that the switch means is turned on based on the set signal to feed back the holding voltage of the sample holder to the capacitor of the charge pump.

Further, it is desirable that the current amounts generated by the charging current source and the discharging current source are adjusted so that their absolute values are substantially the same.

The output voltage of the filter means may be fed back to the capacitor of the charge pump when the switch means is turned on.

Further, voltage coefficient multiplying means for multiplying the holding voltage of the sample holder by a coefficient is provided, and when the switch means is turned on, the holding voltage of the sample holder is multiplied by the voltage coefficient multiplying means to multiply the voltage of the charge pump. Feedback to the capacitor is desirable.

Further, a voltage coefficient multiplying means for multiplying the output voltage of the filter means is provided, and when the switch means is turned on, the output voltage of the filter means is multiplied by a coefficient by the voltage coefficient multiplying means so that Feedback may be provided to the capacitor.

Further, a first voltage coefficient multiplying means for multiplying the holding voltage of the sample holder by a coefficient and a second voltage coefficient multiplying means for multiplying the output voltage of the filter means by a coefficient are provided. Adding means for adding each output voltage of the second voltage coefficient multiplying means and a preset constant voltage is provided, and the output voltage of the adding means is fed back to the capacitor of the charge pump when the switch means is turned on. You may do it.

Further, the edge detecting means may be configured to detect a rising edge and a falling edge of the input data and output an up signal which is set and is cleared at + π point of the cycle.

[0025]

According to the above-described structure, for example, the phase comparison means uses -π with the rising edge position of the clock signal as a reference.
The phase of the edge of the input data detected in the range from to + π is compared with the clock signal. The clock signal itself is used as the down signal for controlling the discharge current source of the charge pump, and the discharge is performed over the period from 0 to + π. The up signal for controlling the charging current source of the charge pump is set by detecting the edge of the input data and is cleared at the time point + π of the cycle of the clock signal. When the detection of input data is performed at time 0 of the clock cycle,
Up and down will occur for the same length of time, the increase and decrease of the charge generated by the charge pump will disappear,
The phase-locked oscillator follows the steady phase.

The charge current source and the discharge current source of the charge pump are controlled by the up signal and the down signal, respectively, but by adjusting so that the absolute values of the current amounts generated by the both current sources are substantially the same, When both current sources are operating at the same time, the change in the charge of the charge pump can be made almost zero. As a result, when the up signal is generated earlier than the rising edge of the clock, the time-difference charge is accumulated, and when the up-signal is late, the time difference discharge is accumulated in the capacitor.

Further, during the period in which both the charging current source and the discharging current source are operating at the same time, the potential of the charge pump does not substantially fluctuate, so that it is possible to detect that both the up and down signals are met. When a signal is generated, the sample holder is activated and the potential at this time is held.

When the edge of the input data is not detected within the period of -π to + π of the clock signal, only the down signal is generated and the charge of the charge pump is unilaterally discharged. At the time of + π, the set signal is output to turn on the switch means, and the voltage held in the sample holder is fed back to the capacitor of the charge pump. As a result, the charge pump
Only the down signal is generated and the voltage is unidirectionally restored to the voltage before the discharge.

The signal output from the sample holder is PL
After passing through a filter that determines the tracking characteristic of L, it is input as the control voltage of the voltage controlled oscillator that is generating the clock signal.

Further, when the switch means is turned on, the output voltage of the filter means is fed back to the capacitor of the charge pump, whereby the transient response of the output voltage of the filter to the change of the holding voltage of the sample holder is interrupted. The fluctuation of the control voltage of the voltage controlled oscillator can be suppressed.

When the switch means is turned on, the holding voltage of the sample holder is multiplied by the coefficient by the voltage coefficient multiplying means and fed back to the capacitor of the charge pump, so that the coefficient can be selected to a value of 0 to 1, for example. For example, when the cycles in which the phase comparison is not performed are continuous, the control voltage of the voltage controlled oscillator gradually converges, and the oscillation of the voltage controlled oscillator converges to a constant state.

Further, when the switch means is turned on, the output voltage of the filter means is multiplied by a coefficient by the voltage coefficient multiplying means and fed back to the capacitor of the charge pump, whereby the transient response of the output voltage of the filter is interrupted and, for example, If the coefficient is selected to a value of 0 to 1, the control voltage of the voltage controlled oscillator gradually converges and the oscillation of the voltage controlled oscillator converges to a constant state when the cycles in which the phase comparison is not performed are continuous.

Further, when the switch means is turned on, the output voltage of the adding means is fed back to the capacitor of the charge pump to select the coefficients of the first and second voltage coefficient multiplying means to values of 0 to 1, respectively. The control voltage of the voltage controlled oscillator can be converged to a preset constant voltage when the cycles in which the phase comparison is not performed are continuous.

Further, the edge detecting means detects the rising edge and the falling edge of the input data and outputs the up signal which is set at the time of the detection and is cleared at the time point + π of the cycle of the clock signal. Both the rising edge and the falling edge of the data can be used for phase comparison, and the frequency of phase comparison can be increased.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of a phase locked oscillator of the present invention.

This PLL circuit compares the phases of the clock signal CLK and the received signal Data, and up (up).
Phase comparator 1 that outputs a signal, a Down signal, a Meet signal, and a Set signal
On the output side of the phase comparator 1, a charge pump 2 that performs a charge / discharge operation by the Up signal and the Down signal and a sample holder 3 that holds the output voltage of the charge pump 2 by the Meet signal are sequentially provided. It is connected.

The charge pump 2 receives the Up signal and D
A charge current source 2a and a discharge current source 2b, which are respectively controlled by the down signal, and a capacitor 2c for accumulating the current generated by the current sources 2a and 2b as electric charges. Is taken out. The current amounts of the two current sources 2a and 2b are set to be substantially equal to each other so that the change in the accumulated charge when the two current sources 2a and 2b are simultaneously operating is substantially zero.

Further, the output side of the sample holder 3 is
It is feedback-connected to the capacitor 2c of the charge pump 2 via the switch 4 that is turned on by the Set signal, and is also connected to the filter 5 that limits the frequency band with respect to changes in the holding voltage of the sample holder 3. The filter 5 that determines the tracking characteristic of the PLL is composed of a low-pass filter (LPF) or the like, and the output side thereof is connected to the VCO 6 that oscillates the clock signal CLK.

FIG. 2 is a circuit diagram showing the internal structure of the phase comparator 1 in FIG.

The phase comparator 1 includes flip-flops 1a,
1b, AND gates 1c and 1d, and delay circuits 1e and 1
f and.

The power supply potential VCC is applied to the data terminal D of the flip-flop 1a, and the reception signal Data is applied to the clock terminal.
However, the clear pulse A1 output from the AND gate 1c is supplied to the clear terminal CLR. An Up signal is output from the output terminal Q1 of the flip-flop 1a.

This flip-flop 1a has a reception signal D.
It is set by the rising edge of ata and cleared by the clear pulse A1. The Up signal is a signal that is set from the time when the edge of the reception signal Data is detected to the time when the clock signal CLK is + π.

The clear pulse A1 is the AND gate 1
c and the delay circuit 1e. Delay circuit 1e
Takes in the clock signal CLK and clear pulse A1
The delay of the required time width is generated as the pulse width of
The D gate 1c uses the clock signal CLK delayed by the delay circuit 1e to generate a trailing edge differential signal of the clock signal CLK. This clear pulse A1 is the clock signal CLK
Occurs at time point + π of.

The Down signal is the clock signal CL.
It is the same signal as K, and the clock signal CLK is from 0 to +
It is set at time π. Then, the AND gate 1d detects that the Up signal and the Down signal are in the set state at the same time, and outputs the Meet signal used as the sampling signal of the sample holder 3.

The Meet signal output from the AND gate 1d is the data terminal D of the flip-flop 1b.
Supplied to Further, the clock signal CLK is supplied to the clock terminal of the flip-flop 1b, the delay circuit 1f is connected between the clear terminal CLR and the output terminal Q2, and the Set signal is output from the output terminal Q2.

This flip-flop 1b is set when it detects that the Meet signal is not generated when the clock signal CLK reaches + π, and outputs the Set signal. This Set signal is output to the capacitor 2c of the charge pump 2 as a signal for activating the switch 4 for field-backing the holding voltage of the sample holder 3 as described above, and holds it for the time required for this feedback operation. After being held for the delay time generated by the delay circuit 1f, it is input to the clear terminal CLR and cleared by itself.

The operation of the present embodiment configured as described above will be described with reference to the operation timing chart of FIG.

As shown in FIG. 3, the Up signal is the clock signal CL from the time when the edge of the received signal Data is detected.
The K signal is set until the time becomes + π, and the Down signal is set from the time when the clock signal CLK is 0 to the time + π.

If the detected edge position of the received signal Data and the phase of the clock signal CLK are aligned, Up / D
The own signals are simultaneously set and held for the same period (time T1, T4, T7, T10 in FIG. 3). The edge position detected from the reception signal Data is the clock signal CL
If it is earlier than the phase of K, the Up signal is set earlier by that amount and held for a longer time than the Down signal (time T2, T3 in FIG. 3). On the contrary, if the edge position detected from the reception signal Data is later than the phase of the clock signal CLK, the Up signal is set later by that amount, and as a result, the Down signal is held longer (time T in FIG. 3).
5, T6).

The Up signal and the Down signal control the charging / discharging operation of the charging current source 2a and the discharging current source 2b of the charge pump 2, respectively. The currents generated by the two current sources 2a and 2b are accumulated in the capacitor 2c as electric charges and taken out as a voltage corresponding to the charge / discharge current amount. As a result, a voltage corresponding to the phase difference detected by the phase comparator 1 is generated in the charge pump 2.

The sample holder 3 samples the voltage generated in the charge pump 2 at this point in response to the output of the Meet signal indicating that the phase difference detection by the phase comparator 1 is completed. Hold its voltage.

The clock signal C whose edges were not detected from the received signal Data and normal phase comparison was not performed
In the LK cycle (the cycle centered on times T8 and T11 in FIG. 3), this Meet signal is not generated, so the voltage held by the sample holder 3 does not change.

In addition, in this cycle, the phase comparator 1 outputs Do
Since only the wn signal is generated, only the discharge current source 2b of the charge pump 2 is activated, and the charge of the capacitor 2c is unilaterally discharged (waveform indicated by X in the figure). If this goes on,
Although the phase comparison is not actually performed, the output voltage of the charge pump 2 is changed, which causes malfunction of the PLL. Therefore, in this embodiment, from −π of the clock signal CLK cycle. Within the period of + π, it is detected that the edge detection from the received signal Data is not performed, the Set signal is output from the phase comparator 1 to turn on the switch 4 (time T9, T12 in FIG. 3), and the sample The holding voltage of the holder 3 is fed back to the capacitor 2c of the charge pump 2. As a result, the charge pump 2 is restored to the voltage before only the down signal is generated and the charges are unilaterally discharged.

According to this embodiment, the switch 4 is turned on and the voltage held in the sample holder 3 is fed back to the capacitor 2c of the charge pump 2 in the period in which the phase comparison is not performed. It is possible to avoid the occurrence of abnormal voltage fluctuation of the charge pump 2 due to the activation of only the current source 2b.

As a result, the PLL circuit can be constructed by using the second phase comparator in place of the first phase comparator described above, so that the charging / discharging completion time of the charge pump 2 is shortened and the reception is completed. The steady phase difference between the edge position of the signal Data and the clock signal CLK generated by the VCO can be set to 0 (the above-mentioned shift of π / 2 does not occur), and the range of the phase difference in which the phase comparator 1 can normally operate is set. It is possible to set within a range of ± π (± π / 2 in the related art) around the rising edge of the clock signal CLK. Further, since the charge pump 2 does not perform the operation of generating the discharge current subsequent to the charge current as in the conventional case, an unnecessary pulsating current component as in the conventional case does not occur in the voltage v of the charge pump 2. .

Further, as is apparent from FIG. 9, conventionally, it takes about 3π / 2 for the average time until the result of the phase comparison is taken into the sample holder and reflected in the voltage v ′. In this embodiment, as is clear from FIG. 3, it becomes as short as about π / 2, and the tracking performance of the PLL is improved.

FIG. 4 is a block diagram showing a main configuration of a PLL circuit according to a second embodiment of the phase locked oscillator of the present invention.

The PLL circuit of this embodiment is the same as the PLL circuit of the first embodiment shown in FIG. 1, but the voltage coefficient multiplying means 1 for multiplying the holding voltage of the sample holder 3 by α (= 0 to 1).
1 is provided, and when the switch 4 is turned on, the sample holder 3
The holding voltage v ′ is multiplied by α by the voltage coefficient multiplying means 11 and is fed back to the capacitor 2c of the charge pump 2.

When the periods in which the phase comparison is not performed are continuous, the control voltage of the VCO 6 changes like an α-times geometric progression. For example, if the coefficient α is selected as a value of 0 to 1, the VCO
The control voltage of 6 gradually converges, and the oscillation of the VCO 6 can be converged to a constant state.

FIG. 5 is a block diagram showing a main configuration of a PLL circuit according to a third embodiment of the phase locked oscillator of the present invention.

The PLL circuit of this embodiment is different from the PLL circuit of the first embodiment shown in FIG. 1 in that voltage coefficient multiplying means 21 for multiplying the output voltage of the filter 5 by β is provided, and the switch 4
Is turned on, the output voltage v ″ of the filter 5 is multiplied by β (= 0 to 1) by the voltage coefficient multiplying means 21 and fed back to the capacitor 2c of the charge pump 2.

According to this embodiment, the transient response of the output voltage v ″ of the filter 5 with respect to the change of the holding voltage of the sample holder 3 can be interrupted, and the fluctuation of the control voltage of the VCO 6 can be suppressed.

Further, for example, if the coefficient β is selected to a value of 0 to 1, the control voltage of the VCO 6 gradually converges and the oscillation of the VCO 6 converges to a constant state when the cycles in which the phase comparison is not performed are continuous. be able to.

FIG. 6 is a block diagram showing a main configuration of a PLL circuit according to a fourth embodiment of the phase locked oscillator of the present invention.

The PLL circuit of this embodiment is the same as the PLL circuit of the first embodiment shown in FIG. 1, but the voltage coefficient multiplying means 1 for multiplying the holding voltage of the sample holder 3 by α (= 0 to 1).
1 and a voltage coefficient multiplying means 21 for multiplying the output voltage v ″ of the filter 5 by β (= 0 to 1), and each output voltage of these voltage coefficient multiplying means 11 and 21 and a preset constant voltage. The addition means 31 for adding E and E is provided, and when the switch 4 is turned on, the output voltage of the addition means 31 is fed back to the capacitor 2c of the charge pump 2.

According to the present embodiment, the control voltage v'of the VOC 6 is set when the cycles in which the phase comparison is not performed are continuous.
′ Gradually converges and can be converged to the constant voltage E. If the constant voltage E is set to the VCO control voltage of the desired oscillation frequency when the PLL circuit is free running, even if the cycle of the clock signal CLK for which phase comparison is not performed is continuous, the oscillation frequency of the PLL circuit is set. Can be controlled arbitrarily.

The present invention is not limited to the above embodiment, and various modifications can be made.

For example, the phase comparator 1 in the above embodiment
The edge detecting means of FIG. 7 detects only the rising edge of the reception signal Data by the flip-flop 1a, but as shown in FIG. 7, the flip-flop 1a- which detects the rising edge and the falling edge of the reception signal Data respectively.
1, 1a-2 are further provided, and an OR gate 1a-3 for taking an OR of these output data is further provided.
You may use the structure which makes the output of a-3 an Up signal. In this case, both the rising edge and the falling edge of the received signal Data can be used for phase comparison, and the frequency of phase comparison can be increased.

The filter 5 may be constituted by the LPF as described above, but the charge pump 2
Since the phase difference signal is accumulated by the capacitor 2c, it is not always necessary to configure the LPF, and the tracking characteristic of the PLL can be arbitrarily changed by using a filter that transmits a signal in a required frequency band. be able to.

[0070]

As described above in detail, according to the present invention, the switch means is turned on and the holding voltage of the sample and hold means is fed back to the capacitor of the charge pump means in the period in which the phase comparison is not performed. Therefore, it is possible to avoid the occurrence of abnormal voltage fluctuation of the charge pump.

As a result, the phase locked oscillator can be constructed by using the second phase comparator instead of the above-mentioned first phase comparator, so that the edge position of the input data and the clock generated by the voltage controlled oscillator. The steady phase difference between and can be set to 0, and the range of the phase difference in which the phase comparator can operate normally is ± π
It is possible to expand to the range of. Further, the unnecessary pulsating flow component as in the conventional case does not occur in the voltage of the charge pump means.

Further, it is possible to shorten the average time taken for the result of the phase comparison to be taken into the sample hold means and reflected in the control voltage of the voltage controlled oscillator, and the tracking performance of the PLL circuit can be improved.

Further, when the switch means is turned on, the output voltage of the filter means is fed back to the capacitor of the charge pump, so that the fluctuation of the control voltage of the voltage controlled oscillator can be suppressed.

Further, when the switch means is turned on, the holding voltage of the sample holder is multiplied by the coefficient by the voltage coefficient multiplying means and fed back to the capacitor of the charge pump. The oscillation of the voltage controlled oscillator can be converged to a constant state.

Further, when the switch means is turned on, the output voltage of the filter means is multiplied by the coefficient by the voltage coefficient multiplying means and fed back to the capacitor of the charge pump to suppress the fluctuation of the control voltage of the voltage controlled oscillator. At the same time, the oscillation of the voltage controlled oscillator can be converged to a constant state when the cycles in which the phase comparison is not performed are continuous.

Further, when the switching means is turned on, the output voltage of the adding means is fed back to the capacitor of the charge pump, so that the control voltage of the voltage controlled oscillator is set in advance when the cycles in which the phase comparison is not performed are continuous. It can be converged to a constant voltage.

Further, the edge detecting means detects the rising edge and the falling edge of the input data and outputs the up signal which is set at the time of the detection and is cleared at the time point + π of the cycle of the clock signal. It is possible to increase the frequency of comparison.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a P according to a first embodiment of a phase locked oscillator of the present invention.
It is a block diagram which shows the structure of a LL circuit.

2 is a circuit diagram showing an internal configuration of a phase comparator 1 in FIG.

FIG. 3 is an operation timing chart of the first embodiment.

FIG. 4 is a diagram illustrating a phase locked oscillator P according to a second embodiment of the invention.
FIG. 3 is a block diagram showing a main configuration of an LL circuit.

FIG. 5 shows a P according to a third embodiment of the phase locked oscillator of the present invention.
FIG. 3 is a block diagram showing a main configuration of an LL circuit.

FIG. 6 shows a P according to a fourth embodiment of the phase locked oscillator of the invention.
FIG. 3 is a block diagram showing a main configuration of an LL circuit.

FIG. 7 is a circuit diagram of a main part of a PLL circuit showing a modified example of the present invention.

FIG. 8 is a block diagram showing a configuration example of a conventional PLL circuit.

FIG. 9 is an operation timing chart of a conventional PLL circuit.

[Explanation of symbols]

 1 Phase Comparator 2 Charge Pump 2a Charging Current Source 2b Discharge Current Source 2c Capacitor 3 Sample Holder 4 Switch 5 Filter 6 VCO 11 Voltage Coefficient Multiplier 21 Voltage Coefficient Multiplier 31 Adder E Constant Voltage CLK Clock Data Received Signal Up Up Signal Down down signal Meet meet signal Set set signal

Claims (8)

[Claims] 1. A phase comparison means for performing phase comparison between the clock signal and input data at regular intervals based on the clock signal, a charging current source which operates based on the phase comparison result of the phase comparison means, Charge pump means having a discharge current source and a capacitor for accumulating charges according to the outputs of these current sources, a sample holder for performing a sample hold operation for holding a voltage generated in the capacitor, and the phase comparing means Switching means that is turned on in a cycle in which phase comparison is not performed and feeds back the holding voltage of the sample holder to the capacitor of the charge pump; and a filter that limits the frequency band with respect to changes in the holding voltage of the sample holding means. Means for controlling the oscillation frequency based on the output voltage of the filter means, Phase locked oscillator, characterized in that a voltage controlled oscillator for outputting a lock signal. 2. The edge detecting means, which detects an edge of the input data, and outputs an up signal which is set at the time of detection and is cleared at a time point of + π of the cycle of the clock signal, the clock signal. The down signal and the up signal, which are output over the period of 0 to + π in the same manner as above, are detected to be output together during the period of −π to + π of the clock signal, and the meet signal is detected. Sampling instructing means for outputting, and a set signal generating means for outputting a set signal when the meet signal is not set at the time point + π of the clock signal, the charge current source and the discharge current source of the charge pump means, The sample holder operates based on the up signal and the down signal, and the sample holder operates based on the meet signal. 3. The phase synchronization according to claim 1, wherein the switch means is turned on based on the set signal to feed back the holding voltage of the sample holder to the capacitor of the charge pump. Oscillator. 3. The phase-locked oscillator according to claim 2, wherein the respective current amounts generated by the charging current source and the discharging current source are adjusted so that their absolute values are substantially the same. 4. The phase-locked oscillator according to claim 1, wherein the output voltage of the filter means is fed back to the capacitor of the charge pump when the switch means is turned on. 5. A voltage coefficient multiplying means for multiplying the holding voltage of the sample holder by a coefficient is provided, and when the switch means is turned on, the holding voltage of the sample holder is multiplied by the voltage coefficient multiplying means to multiply the charge pump. The phase-locked oscillator according to claim 1, wherein the phase-locked oscillator is fed back to the capacitor. 6. A voltage coefficient multiplying means for multiplying the output voltage of the filter means by a coefficient is provided, and when the switch means is turned on, the output voltage of the filter means is multiplied by a coefficient by the voltage coefficient multiplying means to enable the charge pump The phase-locked oscillator according to claim 4, wherein the phase-locked oscillator is fed back to the capacitor. 7. A first voltage coefficient multiplying means for multiplying the holding voltage of the sample holder by a coefficient and a second voltage coefficient multiplying means for multiplying an output voltage of the filter means by a coefficient, and the first and second voltage coefficient multiplying means. Adding means for adding each output voltage of the second voltage coefficient multiplying means and a preset constant voltage is provided, and the output voltage of the adding means is fed back to the capacitor of the charge pump when the switch means is turned on. The phase-locked oscillator according to claim 1 or 2, characterized in that. 8. The edge detecting means detects a rising edge and a falling edge of the input data,
+ Π of the cycle of the clock signal which is set at the time of detection
8. The phase locked oscillator according to claim 2, wherein the phase locked oscillator is configured to output an up signal that is cleared at a time point.