JPH05109768A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To implant an impurity suifficiently selectively in a self-aligned thin film transistor to be manufactured by ion implanting using no mass spectroscopy by coating a conductive film with resist through an inorganic film to be selectively etched, and patterning a gate electrode, etc. CONSTITUTION:A polycrystalline silicon film 103 for a channel is formed on an insulating substrate 101 or an insulating film 102, and a conductive film 105 for a gate electrode is deposited thereon through a gate insulating film 104. Then, after a conductive film 105 and an inorganic film 106 to be selectively etched are formed on the film 105, it is coated with resist 107, and the electrode is patterned by using a photoetching method. Thereater, with the electrode and the resist 107 as masks impurity ions are implanted by using an ion implanting unit using no mass spectroscopy thereby to form source, drain regions, the film 106 is then etched to peel the resist 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art As one of the methods for manufacturing a self-aligned thin film transistor formed on a large area, there is a method using an ion implantation method which does not use mass spectrometry. However, the above method has a drawback that the substrate temperature rises because the large area is irradiated with the ion beam. Therefore, if a resist mask used in a usual method for manufacturing a semiconductor device is used, the resist is fixed due to heat and ion damage. As a means to prevent this, it was considered to remove the insulating film above the source / drain and implant with low energy, but with this method, the breakdown voltage between the gate and the drain or the source part deteriorates and reliability is reduced. Lack. In addition, it was considered that an inorganic film was deposited instead of the resist to form an ion mask, but with this method, it is difficult to deposit it to a thickness sufficient to function as an ion mask, or a sufficient thickness is required. However, there is a defect that the characteristics of the thin film transistor are deteriorated.

[0003]

DISCLOSURE OF THE INVENTION To devise an ion mask and a mask removing method capable of sufficiently selective impurity implantation in a self-aligned thin film transistor manufactured by using an ion implantation technique without mass spectrometry. is there.

[0004]

A method of manufacturing a thin film transistor according to the present invention is for solving the above-mentioned problems, and is a channel in a self-aligned thin film transistor formed on an insulating substrate or an insulating film. A step of forming a polycrystalline silicon film, a step of forming a gate insulating film on the polycrystalline silicon film, and a step of depositing a first conductive film to be a gate electrode on the gate insulating film,
Forming a second inorganic film that is selectively etched with the conductive film on the conductive film; applying a resist and patterning the gate electrode using a photo-etching method; And a step of forming source / drain regions by implanting impurity ions using an ion implantation apparatus that does not use mass spectrometry using the resist as a mask, and a step of removing the resist by etching the second inorganic film. It is characterized by including.

[0005]

EXAMPLE 1 FIG. 1 is a process chart of an example showing a method of manufacturing a thin film transistor according to the present invention. Figure 1
As shown in (a), first, a silicon oxide film 102 as an insulating film is deposited to a thickness of 2000 Å on a glass substrate 101. The purpose of the insulating film is to prevent heavy metals contained in the glass substrate from diffusing into the element portion during the heat treatment, and it is not necessary that the purity of the glass substrate is sufficiently high. Next, the non-doped polycrystalline silicon 103 is added from 250 Å to 5
Deposit and pattern to any thickness between 00Å. Next, a silicon oxide film 104 is deposited to a thickness of 1500 Å as a gate insulating film. Next, the metal Cr105 is 1
Deposit with a thickness of 500Å. Next, Al 106 5000
Deposit with a thickness of Å. Next, as shown in FIG. 1B, a resist 107 is applied in a thickness of about 1 to 2 μm, and the resist is patterned by a photolithography method. Subsequently, Al 106 is etched, and further Cr10
5 is etched to form a gate electrode. Next in FIG.
As shown in (c), an ion beam 108 containing phosphorus ions was used for 11
Phosphorus is implanted in an amount of 3 × 10 ¹⁵ / cm ² or more at an energy of 0 keV to form the source / drain regions 109 in a self-aligned manner. Next, nitrogen annealing is performed at 300 ° C. for 2 hours to activate the impurities. Next, as shown in FIG. 1D, Al 106 is etched to form a resist 107.
To remove. Next, as shown in FIG. 1 (e), a silicon oxide film 110 is deposited as an interlayer insulating film to a thickness of 5000Å, contact holes are opened in the source / drain regions, and Al111 is used for electrode wiring.

(Embodiment 2) FIG. 2 is a process drawing of another embodiment showing a method of manufacturing a thin film transistor according to the present invention. First, as shown in FIG. 2A, a silicon oxide film 20 as an insulating film is formed on a substrate 201 such as a glass substrate or a quartz substrate.
2 is deposited to a thickness of 2000Å. The purpose of the insulating film is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary that the purity of the substrate is sufficiently high. Next, polycrystalline silicon 2 containing no impurities
03 is deposited to a desired thickness between 250 Å and 500 Å and patterned. Next, remove the silicon oxide film 1500
A gate insulating film 204 is formed by depositing with a thickness of Å. Next, Ta205 is deposited to a thickness of 3000 Å. Next, Cr or Al 206 is deposited to a thickness of 1000Å. Next, as shown in FIG.
It is applied to a thickness of about μm and the resist is patterned by photolithography. Then Cr or A
1206 is etched and Ta205 is further etched to form a gate electrode. Next, as shown in FIG. 2 (c), an ion implanter that does not use mass spectrometry is used so that the ion beam 208 containing phosphorus ions is 110 keV and the amount of phosphorus is 3 × 10 ¹⁵ pieces / cm ² or more. Implantation is performed to form source / drain regions 209. Then 30
The impurities are activated by thermal annealing at 0 ° C. or 350 ° C. for 1 hour. Next, as shown in FIG.
Etching 206 removes the resist 207. Next, as shown in FIG. 2E, a silicon oxide film 210 is deposited as an interlayer insulating film to a thickness of 5000 Å, contact holes are opened in the source / drain regions, and Al or I is formed.
Electrode wiring is performed at TO211.

[0007]

The present invention has the following effects.

(1). By using a sufficiently thick ion mask, implantation into the channel portion can be prevented and the characteristics of the thin film transistor are stabilized.

(2). For the first time, an ion implanter that does not use high-energy mass spectrometry can be used.

(3). It is possible to reduce the thickness of the gate electrode, so that it is possible to prevent the disconnection defect of the source line intersecting with the gate line.

[Brief description of drawings]

FIG. 1 is a process drawing showing an embodiment of a method of manufacturing a thin film transistor of the present invention.

FIG. 2 is a process drawing showing an example of a method of manufacturing a thin film transistor of the present invention.

[Explanation of symbols]

 101 substrate 102 silicon oxide film 103 non-doped polycrystalline silicon 104 silicon oxide film 105 Cr 106 Al 107 resist 108 ion beam 109 source / drain region 110 silicon oxide film 111 Al 201 substrate 202 silicon oxide film 203 polycrystalline silicon 204 silicon oxide film 205 Ta 206 Cr or Al 207 Resist 208 Ion Beam 209 Source / Drain Region 210 Silicon Oxide Film 211 Electrode Wiring

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display area H01L 27/12 8728-4M

Claims (1)

[Claims] 1. A self-aligned thin film transistor formed on an insulating substrate or insulating film, comprising a step of forming a polycrystalline silicon film to be a channel, and a step of forming a gate insulating film on the polycrystalline silicon film. Depositing a first conductive film to be a gate electrode on the gate insulating film, and forming a second inorganic film selectively etched with the conductive film on the conductive film And a step of applying a resist and patterning a gate electrode by using a photo-etching method, and using the gate electrode and the resist as a mask to implant impurity ions using an ion implantation apparatus without mass spectrometry A thin film characterized by including a step of forming a region and a step of removing the resist by etching the second inorganic film. Method of manufacturing a membrane transistor.