JPH11111634A - Forming of n-type semiconductor film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a thin film of N-type polysilicon, in which the recovery of the crystallinity from a damaged state and the activation of implanted impurity ions can be achieved with an annealing process at a relatively low temperature by sequentially forming a polysilicon film and an insulator film, each having a specified thickness, on an insulating substrate, and elements including group-V element ions are implanted into the polysilicon film through the insulator film. SOLUTION: On a glass substrate 101, an amorphous silicon film of 50-150 nm in thickness is deposited and is annealed to make a polysilicon film 103. Then, the polysilicon film is partly etched off to form an island 104 of polysilicon film, onto which a gate insulating film 106 of 50-150 nm in thickness is formed, and a gate electrode 107 is formed on the film 106. Ions 108 of including group-V elements are implanted into the polysilicon film self-alignedly by utilizing the gate electrode 107 as the mask for the ion implantation. By annealing the implanted polysilicon film at a temperature ranging 300-500 deg.C, the implanted group-V element ions are activated to make the implanted film regions N-type polysilicon form a drain region 109S and a source region 109D of a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an N-type semiconductor film, and more particularly to a method for forming an N-type semiconductor film by performing a heat treatment at a low temperature to reduce distortion of a glass substrate.

[0002]

2. Description of the Related Art In recent years, development for manufacturing a drive circuit such as a liquid crystal display or an image sensor on the same substrate as a display or an image sensor has been advanced. For that purpose, it is necessary to manufacture a thin film transistor on a commonly used inexpensive glass substrate.

When a glass substrate is used, it is necessary to process at a temperature that does not affect the glass substrate. Usually, non-alkali glass is used in consideration of the influence on impurities in the semiconductor device. Barium borosilicate glass (such as # 7059 manufactured by Corning), borosilicate glass (such as AN manufactured by Asahi Glass), aluminoborosilicate glass (such as # 1735 manufactured by Corning), aluminosilicate glass (NA40 manufactured by HOYA) Etc.) are used. However, the strain point of such a glass substrate is about 593 to 700 ° C., and the temperature which can be actually used is 700 ° C. or less, so that the treatment at 700 ° C. or less is required.

[0004]

However, the source / drain portions of the thin film transistor are usually formed by implanting impurity ions and then recovering crystal damage caused by the implantation and activating the impurity ions. It is necessary to perform high temperature heat treatment. Usually, a polycrystalline silicon film which is a semiconductor film must be heat-treated at a temperature exceeding 500 ° C.

For example, furnace annealing requires a treatment at 600 ° C. for several hours, but this causes a problem that the glass substrate is thermally shrunk. In some cases, a short time is acceptable, but in a few hours, it becomes a problem. When the glass substrate shrinks, misalignment occurs in photolithography for manufacturing a device, so that a good device cannot be manufactured.

In the laser annealing method, since the surface of the polycrystalline silicon film can be treated at a high temperature while keeping the glass substrate at a low temperature, the influence on the glass substrate can be reduced, but there is a problem of poor uniformity. A commonly used excimer laser is a pulse laser and has a limited beam size. Therefore, when irradiating a large area, the beams must be jointly irradiated. Since the film quality of the polycrystalline silicon film changes at the spliced portion to have different characteristics, good uniformity cannot be ensured.

Further, the lamp annealing method has a problem that the glass substrate is warped or cracked.

The present invention solves the above-mentioned problems and provides a method of forming an N-type semiconductor film which can recover crystal damage and activate impurity ions at a low temperature and has good performance. With the goal.

[0009]

In order to achieve the above object, a method for forming an N-type semiconductor film according to the present invention comprises the steps of forming a polycrystalline silicon film having a thickness of 50 to 150 nm on an insulating substrate. A film thickness of 50 to 15 on the polycrystalline silicon film.
Forming a 0 nm insulating film; implanting an element containing a Group V element into the polycrystalline silicon film through the insulating film; and performing a heat treatment at a temperature of 300 to 500 ° C.

[0010] The element containing a Group V element may be a Group V element such as phosphorus and hydrogen.

Next, the operation of the present invention will be described. Since the Group V element such as phosphorus is implanted into the polycrystalline silicon film through the insulating film having a thickness of 50 to 150 nm, crystal damage of the polycrystalline silicon film at the time of implantation is reduced. In addition, since the thickness of the polycrystalline silicon film is 50 nm or more, a region where crystal damage does not occur in the thickness direction remains. Therefore, the heat treatment temperature for recovering crystal damage after implantation and for activating impurity ions such as phosphorus is 300 to 5 hours.
Distortion of an insulating substrate such as glass can be prevented well at a low temperature of 00 ° C. The thickness of the polycrystalline silicon film is set to 150
The reason why the thickness is set to nm or less is that if the thickness is too large, the performance of a semiconductor as a product is deteriorated. Further, when hydrogen is implanted together with the group V element, the degree of amorphization of the polycrystalline silicon film can be reduced.

Further, when the thickness of the polycrystalline silicon film is 7
0 to 150 nm, and the thickness of the insulating film is 70 to 150 nm
Is more preferable because the effect of reducing the degree to which the polycrystalline silicon film is made amorphous is greater.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for forming an N-type semiconductor film according to the present invention will be described below with reference to the drawings. FIGS. 1, 2 and 3 are schematic cross-sectional views showing steps of manufacturing a semiconductor film of the present invention. FIG. 1 shows a film pressure of 5 on an insulating substrate.
After forming a polycrystalline silicon film having a thickness of 0 to 150 nm and forming an insulating film having a thickness of 50 to 150 nm on the polycrystalline silicon film, the polycrystalline silicon film contains a Group V element through the insulating film. It is a schematic sectional drawing which shows the process of implanting ions. 1 is an insulating substrate, 2 is a polycrystalline silicon film,
Reference numeral 3 denotes an insulating film, and reference numeral 4 denotes ions containing Group V element ions. FIG. 2 is a schematic cross-sectional view showing that an amorphous region 5 is formed in the polycrystalline silicon film 2 by implanting ions including Group V element ions. By setting the thicknesses of the polycrystalline silicon film 2 and the insulating film 3 as described above, the crystal nuclei of the polycrystalline silicon are left, the rate of amorphization in the polycrystalline silicon film 2 is relaxed, and activation at a low temperature is achieved. Can be created. FIG.
It is a schematic sectional drawing after heat processing at the temperature of -500 degreeC.
Reference numeral 6 denotes an N-type polycrystalline silicon film in which the implanted Group V element is activated, and is easily activated by a low-temperature heat treatment at a temperature not exceeding 500 ° C. Thereby, a good N-type polycrystalline silicon film can be obtained.

Next, the operation of the present embodiment will be described. FIG.
As shown in FIG. 5, when implanting impurity ions 4 containing Group V element ions into the polycrystalline silicon film 2 through the insulating film 3, it is necessary to implant relatively high energy ions.
At this time, the crystal of the polycrystalline silicon film 2 is broken from the vicinity of the interface between the insulating film 3 and the polycrystalline silicon film 2 toward the insulating substrate, and becomes amorphous. For example, a polycrystalline silicon film 2 having a thickness of 50 nm is doped with phosphorus (P) of a group V element.
In order to perform implantation through a silicon oxide film (insulating film 3) having a thickness of 50 nm, it is theoretically necessary to implant phosphorus having energy of about 50 to 70 keV. When such high-energy ions are implanted at a dose of about 1E15 to 1E16 / cm <2> at a concentration required for device fabrication, the crystals in the polycrystalline silicon film are destroyed. When the thicknesses of the polycrystalline silicon film and the insulating film are less than 50 nm, the level of crystal destruction in the polycrystalline silicon film is extremely large as shown in FIG. Become. In such a state, even after the heat treatment at a low temperature of 300 to 500 ° C., the amorphous silicon film 8 containing the group V element is obtained as shown in FIG. Can not.
Therefore, this does not result in a good semiconductor film, so that a device with good performance cannot be manufactured.

However, if the thicknesses of the polycrystalline silicon film and the silicon oxide film as the insulating film are 50 nm or more,
As shown in FIG. 2, there can be crystals remaining without being destroyed in the polycrystalline silicon film 2 (particularly, on the insulating substrate 1 side in the polycrystalline silicon film 2).
Even by a heat treatment at a low temperature of 300 to 500 ° C. which does not exceed 0 ° C., the broken crystal is recovered and the group V element is activated in the silicon film. This effect was not remarkably observed when the thicknesses of the polycrystalline silicon film 2 and the insulating film 3 were less than 50 nm. Further, when the thickness of the insulating film 3 is less than 50 nm, the electric breakdown voltage of the insulating film is insufficient, so that it cannot be applied to a device. In particular, for the above reasons, when the film thickness of the polycrystalline silicon film 2 and the insulating film 3 is 70 nm or more, a very remarkable effect is observed, and when the film is applied to a device, it is very effective. The thickness is preferably 70 nm or more.

Further, when a hydrogen element is simultaneously implanted in the step of implanting a group V element, the degree of amorphization of the polycrystalline silicon film 2 can be reduced, and the effect of activation at a low temperature can be obtained. Can be promoted.

The polycrystalline silicon film 2 and the insulating film 3
When the film thickness exceeds 150 nm, good performance cannot be obtained when a device is manufactured by this, so the film thickness is preferably 150 nm or less. For example,
When a thin film transistor is manufactured using this semiconductor film, if the thickness of the polycrystalline silicon film 2 as the active layer exceeds 150 nm, the off-state characteristics of the transistor deteriorate. Also,
When the insulating film 3 also functions as a gate insulating film in a transistor, a thickness exceeding 150 nm is not preferable because the threshold voltage of the transistor increases and the performance deteriorates.

As described above, it is understood that the thicknesses of the polycrystalline silicon film 2 and the insulating film 3 are preferably within the range A shown in FIG. The effect is particularly remarkable in the range B, which is particularly preferable.

[0019]

Next, a method of forming a thin film transistor as an example of a method of forming a semiconductor film according to the present invention will be described. FIG.
(A) to (h) are schematic sectional views showing examples of the thin film transistor of the present invention. As shown in FIG. 7A, an amorphous silicon film having a thickness of 50 to 150 nm is formed on a glass substrate 101 at a substrate temperature of 450 ° C. using a Si 2 H 6 gas by a low pressure CVD method. In particular, preferably the film thickness is 70
１５０150 nm. Although a glass substrate was used here,
Substrates such as a quartz substrate and a sapphire substrate can also be used. The use of a glass substrate is preferable because it is inexpensive and the device cost for manufacturing can be reduced.
In addition, a substrate in which an insulating film is formed over these substrates or a silicon wafer can be used. This insulating film includes a silicon oxide film, a silicon nitride film, aluminum oxide,
A single film of tantalum oxide or the like or a stack of two or more kinds can be used.

The method for forming the amorphous silicon film is not particularly limited, but other methods such as a plasma CVD method and a sputtering method can be used. Since a good quality polycrystalline silicon film can be obtained after annealing by performing the depressurized CVD method, the depressurized CVD method is used here. The substrate temperature is preferably from 400 to 600 ° C., and SiH4 may be used as a source gas.

Next, as shown in FIG. 7B, annealing and crystallization are performed first to form a polycrystalline silicon film 103. Here, furnace annealing is performed at 600 ° C. in a nitrogen atmosphere.
For 24 hours for crystallization. The annealing method is not particularly limited, but furnace annealing, laser annealing, lamp annealing, electron beam annealing, or a combination thereof can be used. Here, furnace annealing with good uniformity was used. Annealing temperature 500 ~ in nitrogen atmosphere
The annealing can be performed at 650 ° C. for 4 to 24 hours.

Next, as shown in FIG. 7C, the polycrystalline silicon film is etched to form an island-shaped polycrystalline silicon film 1.
04 is formed. Here, a patterned resist was formed by a commonly used photolithography technique, and the polycrystalline silicon film was etched by a dry etching method using plasma.

Next, as shown in FIG. 7D, a gate insulating film 106 is formed. Gate insulating film is plasma CVD
100 nm thick silicon oxide (Si) formed by using a TEOS (tetraethylorthosilicate: Si (OC ₂ H ₅ ) ₄ ) gas and an O ₂ gas at 350 ° C.
O ₂ ) film was used. Here, the above-described method was used.
Plasma CVD using H ₄ gas and O ₂ gas, 45
0 pressure CVD method and using SiH ₄ gas and O ₂ gas at ° C., atmospheric pressure C using SiH ₄ gas and O ₂ gas at 430 ° C.
Needless to say, a silicon oxide film formed by a VD method, a sputtering method, or the like may be used. Membrane pressure is 50-150
nm. In particular, the film pressure is preferably set to 70 to 150 nm. Although a silicon oxide film is used here, a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film may be used.

Next, as shown in FIG. 7E, a gate electrode 107 is formed. Polycrystalline silicon film, Al, AlS
i, AlTj, TiN, Ti, Ta, TaN, Cr, W
Alternatively, after forming these stacked films, they are formed by etching.

Next, as shown in FIG. 7F, ions 108 containing a group V element are implanted into the polycrystalline silicon film in a self-aligned manner using the gate electrode 107 as a mask.
Activating the impurity ions to form the source 10 of the transistor
9S, a drain portion 109D is formed. At this time, the portion not implanted with impurities is the channel portion 1 of the transistor.
09C. In the source / drain portion, by setting the thicknesses of the polycrystalline silicon film and the insulating film as described above, the crystal nuclei of the polycrystalline silicon are left and the rate of amorphization in the polycrystalline silicon film is reduced. A state that can be activated at a low temperature can be created. After this, 300-500 ° C
Is heat-treated at the above temperature, the source / drain portion becomes an N-type polycrystalline silicon film in which the group V element is activated. Thus, it is easily activated by a low-temperature heat treatment at a temperature not exceeding 500 ° C. Thereby, a good N-type polycrystalline silicon film can be obtained in the source / drain portions.

Next, as shown in FIG. 7G, an interlayer insulating film 110 nm is formed. Here, the interlayer insulating film 110
Is a film pressure 50 formed at 300 ° C. by plasma CVD.
A 0-nm silicon nitride film was used. Plasma CVD using TEOS gas with good step coverage,
Needless to say, a silicon oxide film formed by the VD method may be used. The thickness is preferably about 300 to 500 nm.

Next, as shown in FIG. 7 (h), after opening contact holes 111S and 111D, a source wiring 112 and a drain wiring 112D were formed, and a thin film transistor was manufactured. Thus, according to the present invention,
The step of activating the source / drain portions is easy, and a transistor having good characteristics can be obtained.

Hereinafter, the experimental data which is the basis for limiting the numerical values and which is set forth in the claims of the present invention will be described.

FIG. 8 shows the relationship between the sheet resistance and the thickness of the polycrystalline silicon film. The film thickness of the insulating film is 100 nm
The sheet resistance value was determined by changing the thickness of the polycrystalline silicon film between 30 and 200 nm. The polycrystalline silicon film implanted with phosphorus ions is
The sheet resistance of the polycrystalline silicon film after the heat treatment for 1 hour was evaluated. The energy of phosphorus ions to be implanted is 100k
eV. Sheet resistance is 5 to make device
kΩ / □ or less, preferably 1 kΩ / □ or less. Therefore, from this figure, it is sufficient that the thickness of the polycrystalline silicon film is 50 nm or more, preferably 70 nm.
That is all.

FIG. 9 shows the relationship between the sheet resistance and the thickness of the insulating film. The thickness of the polycrystalline silicon film is 100 nm
The sheet resistance value was determined by changing the thickness of the insulating film between 30 and 200 nm. The sheet resistance of the polycrystalline silicon film after the heat treatment of the polycrystalline silicon film into which phosphorus ions were implanted at 400 ° C. for 1 hour was evaluated. At this time, the energy of the phosphorus ions to be implanted is changed according to the thickness of the insulating film. The projection range of the implanted phosphorus ions was changed so as to be approximately at the interface between the insulating film and the polycrystalline silicon film. A silicon oxide film was used as the insulating film. For example, when the thickness of the insulating film is 30 nm, 30 keV, 50 n
50 keV at m, 70 keV at 70 nm, 10
At 0 nm, it was set to 100 keV. In order to fabricate a device, the sheet resistance only needs to be 5 kΩ / □ or less.
It is preferably 1 kΩ / □ or less. Therefore, the thickness of the insulating film may be 50 nm or more, and is preferably 70 nm or more.
-150 nm.

FIG. 10 shows the relationship between the sheet resistance and the heat treatment temperature. When the thickness of the insulating film is 100 nm and the thickness of the polycrystalline silicon film is 70 nm, the heat treatment temperature is set to 200 to
The temperature is changed between 600 ° C. and the heat treatment time is set to 0.5 to 5.0.
h and the sheet resistance was evaluated. The processing time is preferably 2 hours or less in consideration of mass productivity.
Therefore, it is understood that the heat treatment temperature needs to be 300 ° C. or more in order to achieve the above-described sheet resistance within the processing within 2 hours.

Further, as shown in FIG. 7, it is necessary to heat-treat after manufacturing a gate electrode and the like when manufacturing a device. There is a great demand to use low-resistance aluminum for the gate electrode. However, aluminum has a low melting point, and is difficult to use at temperatures of 500 ° C. or higher. Therefore, it is desired that this heat treatment be performed at 500 ° C. or lower.

The present invention is not limited to the embodiments and examples described above, and various changes can be made without departing from the gist of the invention.

[0034]

As described above, according to the method of forming an N-type semiconductor film of the present invention, a polycrystalline silicon film having a thickness of 50 to 150 nm is formed on an insulating substrate, and a film thickness is formed on the polycrystalline silicon film. By forming an insulating film of 50 to 150 nm,
When ions including Group V element ions are implanted into the polycrystalline silicon film through the insulating film, the degree to which the polycrystalline silicon film becomes amorphous can be reduced,
Thereby, the heat treatment at a low temperature of 300 to 500 ° C. can activate the group V element and recover crystal damage in the silicon film, so that a problem such as heat shrinkage of the glass substrate does not occur and a favorable condition is obtained. It has excellent effects such as the ability to form an N-type semiconductor film having high performance.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a step of implanting ions containing a group V element into a polycrystalline silicon film.

FIG. 2 is a schematic cross-sectional view of the present invention showing a state after ions including a group V element are implanted into a polycrystalline silicon film.

FIG. 3 is a schematic sectional view of the present invention showing a state after heat treatment at a temperature of 300 to 500 ° C.

FIG. 4 is a schematic cross-sectional view showing a state after ions including a group V element have been implanted into a polycrystalline silicon film when not according to the present invention.

FIG. 5 is a schematic cross-sectional view showing a state after a heat treatment at a temperature of 300 to 500 ° C. when not according to the present invention.

FIG. 6 is a diagram showing a range of the thicknesses of a polycrystalline silicon film and an insulating film according to the present invention.

FIGS. 7A to 7H are schematic cross-sectional views illustrating an embodiment of a thin film transistor to which the method for forming a semiconductor film according to the present invention is applied.

FIG. 8 is a diagram showing a relationship between a sheet resistance and a thickness of a polycrystalline silicon film.

FIG. 9 is a diagram illustrating a relationship between a sheet resistance and a film thickness of an insulating film.

FIG. 10 is a diagram showing the relationship between sheet resistance and heat treatment temperature.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating substrate 2 polycrystalline silicon film 3 insulating film 4 ions containing group V element ions

Claims (2)

[Claims] 1. A film having a thickness of 50 to 150 nm on an insulating substrate.
Forming a polycrystalline silicon film, forming an insulating film having a thickness of 50 to 150 nm on the polycrystalline silicon film, and applying a group V element ion to the polycrystalline silicon film through the insulating film. Implanting ions comprising
Performing a heat treatment at a temperature of 0 to 500 ° C. 2. The method for forming an N-type semiconductor film according to claim 1, wherein said ions containing a Group V element are Group V element ions and hydrogen ions.