JPH06260500A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To prevent chemical reactions of an insulating film without a drop in doping yield by performing a doping process with a gate oxide remaining and then activating the dopant by laser after the removal of the oxide. CONSTITUTION:The other areas than a semiconductor silicon region 12 is covered with photoresist 15. Impurity is introduced to the silicon region by plasma doping with the photoresist and a gate electrode used as masks. After the doping, the exposed silicon oxide is etched with the photoresist mask 15 remaining. Then, the photoresist mask is removed and the impurity is activated by laser irradiation. A silicon oxide film 17 is formed as an insulator by plasma CVD, and multilayer interconnections 18a and 18b are formed with contact holes in the oxide film. Finally, annealing is carried out to form an NMOS circuit.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
FT) structure and manufacturing method. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, when a thin film transistor (top gate type TFT) in which a gate is located on an active layer is manufactured by using laser crystallization or laser activation technology (including flash lamp annealing), After patterning the thin film semiconductor region (active layer) into an island shape, an insulating film is formed as a gate insulating film by a CVD method or a sputtering method, and a gate electrode is formed on the insulating film. Irradiating a doping impurity (dopant) to form impurity regions such as a source region and a drain region in the semiconductor region in a self-aligned manner (using the gate electrode as a mask), and then performing laser irradiation, so that the semiconductor is first formed. The impurities introduced therein were activated (laser activation).

[0003]

However, there are some problems in such a conventional method. One is that, during laser activation, some of the impurities in the semiconductor react with the gate insulating film material (such as silicon oxide) that is present thereon, forming compounds such as phosphorus glass and boron glass. Also, due to the non-equilibrium chemical reaction, a non-stoichiometric semiconductor oxide (such as silicon oxide in which the ratio of oxygen and silicon is not 2: 1) is generated, and the contact resistance is high when the contact is formed later. Was to be. Further, the surface irregularities were remarkable due to the above reaction and the like. Therefore, the yield was reduced. The other is that the boundaries of the regions doped with impurities are shadows of the gate electrode portion, the activation of the boundaries is insufficient, the characteristics are unstable, and the reliability is deteriorated. An example will be described below.

FIG. 5 shows an example of a conventional laser activation technique. First, a base insulating film (silicon oxide or the like) is formed on the substrate 50.
51 is deposited, and then an island-shaped crystalline semiconductor region (silicon or the like) 52 is formed. In addition, CVD
A gate insulating film (silicon oxide or the like) 53 is formed by a method such as sputtering or sputtering, and a gate electrode (phosphorus-doped silicon, aluminum, tantalum, or the like) 54 is further formed. (Figure 5 (A))

After doping the impurities, strong light such as a laser is irradiated to activate the impurity regions 55a and 55b. In this case, due to the momentary high temperature state, a chemical reaction occurs at the interface between the semiconductor and the gate insulating film indicated by P in the figure, and the insulating film material such as phosphorus glass (or boron glass) as previously pointed out. Dopant materials combine. Further, silicon oxide and silicon are combined to generate silicon oxide having a non-stoichiometric ratio. (Fig. 5 (B))

FIG. 6 also shows an example of the conventional laser activation technique, but unlike the case of FIG. 5, an anodic oxide 65 of the gate electrode is formed around the gate electrode. Such an anodic oxide causes an offset state in which the gate electrode and the impurity (to be introduced) region are separated from each other by a distance X, and the electrical characteristics of the TFT (leakage current when reverse biasing the gate, etc.) Can be improved.
(Fig. 6 (A))

However, in this case, Q in FIG.
In the area as shown in, the crystallinity is destroyed by the high-speed doping impurities, but the activation of the laser beam is not performed because the irradiation of the laser beam is not sufficient, and many trap levels are generated, which deteriorates the TFT characteristics. Sex decreases. (FIG. 6 (B)) An object of the present invention is to solve such a problem.

[0008]

According to the present invention, the above problems are solved by performing doping with the gate insulating film attached, and removing the gate insulating film for activation in the subsequent laser activation step. To do. However, when removing the gate insulating film, the underlying oxide film and the substrate are likely to be etched at the same time.
The present invention is characterized in that a mask is used for introducing impurities, and then the gate insulating film and the like are selectively etched using the mask.

As a result, it was possible to prevent the reaction between the semiconductor and the insulating film in the laser activation step without lowering the yield during doping.
Further, in a TFT having a structure in which an offset is provided by using an anodic oxide as shown in FIG. 6, if a part of the anodic oxide is simultaneously etched in the step of etching the gate insulating film, it is doped. It is also possible to irradiate the laser on the boundary between the different regions. Hereinafter, the present invention will be described in more detail with reference to examples.

[0010]

[Embodiment] [Embodiment 1] FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. A base film 11 of silicon oxide having a thickness of 2000Å was formed on a substrate (Corning 7059) 10 by sputtering. Further, an amorphous silicon film having a thickness of 200 to 2000 Å, for example 1500 Å, was deposited by the plasma CVD method. Subsequently, a silicon oxide film having a thickness of 200 to 1000 Å was deposited as a protective film by a sputtering method. Then, this was annealed in a reducing atmosphere at 500 to 600 ° C., for example, 600 ° C. for 48 hours for crystallization. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form the island-shaped silicon region 12.

Next, a thickness of 85 is formed by the sputtering method.
A silicon oxide film 13 having a thickness of 0 to 1500 Å, for example, 1000 Å is deposited as a gate insulating film, and subsequently, a thickness of 6000 to 8000 Å, for example, 6000 is formed by a low pressure CVD method.
A Å silicon film (containing 0.01 to 2% phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film was patterned to form the gate electrode 14. (Fig. 1
(A))

Next, after masking a region other than the semiconductor region 12 with the photoresist 15, a photoresist mask 15 is formed on the silicon region 12 by a plasma doping method.
Then, impurities (phosphorus) were implanted using the gate electrode 14 as a mask. The doping pattern at this time is shown in FIG.
The shape is as shown in. As a doping gas,
Using phosphine (PH ₃ ), the acceleration voltage is 60-11
It was set to 0 kV, for example, 80 kV. The dose is 1 × 10 ¹⁵
˜5 × 10 ¹⁵ cm ⁻² , for example 1 × 10 ¹⁵ cm ⁻² .
As a result, N-type impurity regions 16a and 16b were formed in self-alignment with the gate electrode 14. (Fig. 1
(B))

After the impurity doping step was completed, the exposed portion of the silicon oxide film 13 was etched by etching with hydrofluoric acid with the mask 15 still attached. At this time, it should be noted that the silicon oxide 11 of the base insulating film is also partially etched. After the etching process was completed, the resist was peeled off.

After that, the impurities were activated by laser irradiation. As the laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 to 40 nsec) was used, but in addition, a XeF excimer laser (wavelength 35
3nm), XeCl excimer laser (wavelength 308n
m), ArF excimer laser (wavelength 193 nm), etc. may be used. The energy density of the laser is 250
˜400 mJ / cm ² , for example 300 mJ / cm ^2, and ² to 10 shots, for example 2 shots, may be applied to one location. Substrate 200 to 4 during laser irradiation
You may heat to about 50 degreeC. It should be noted that the optimum laser energy density changes when the substrate is heated. (Fig. 1 (D))

After activation of the impurities, a thickness of 5000
~ 8000 Å, for example 6000 Å, a silicon oxide film 17 is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in this, and a metal material such as titanium nitride (1000 to 2000 Å, for example 1000 Å)
And aluminum (5000-10000Å, for example 80
The wirings 18a and 18b were formed of a multi-layer film of 00Å). Then, in a hydrogen atmosphere at 0.1 to 1 atmosphere and 250 to 400 ° C., for example, 1 atmosphere and 350 ° C., for 30 to 120 minutes,
For example, annealing was performed for 30 minutes. Through the above steps, the NMOS semiconductor circuit is completed. (Fig. 1 (E))

[Embodiment 2] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
An underlayer film 21 of silicon oxide having a thickness of 2000 Å was formed on the substrate 0 by sputtering. Further, by the plasma CVD method, the thickness is 200 to 2000Å, for example, 1000Å
Deposited an amorphous silicon film. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form the island-shaped silicon region 22. The size of one island-shaped silicon film was 30 μm × 30 μm.

Next, a thickness of 80 is obtained by the sputtering method.
A silicon oxide film 13 having a thickness of 0 to 1500 Å, for example, 1000 Å is deposited as a gate insulating film, and subsequently, a thickness of 3000 to 6000 Å, for example, 60 is formed by a sputtering method.
A 00Å aluminum film (containing 2% silicon) was deposited. It is desirable to add 0.5 to 5% of silicon or 0.2 to 2% of copper to aluminum. This is a later step, because there is a heat treatment at 250 to 350 ° C,
This is because hillocks are generated if these impurities are not contained. It should be noted that it is desirable to continuously perform the film forming process of silicon oxide and aluminum. Further, after the aluminum film was formed, heat treatment at 100 to 300 [deg.] C. could suppress the generation of hillocks.

Then, the aluminum film was etched with phosphoric acid to form a gate electrode 24. Furthermore, after applying photo-nice (photosensitive polyimide), patterning is performed, and the temperature is 250 to 350 ° C., for example, 300 ° C.
Bake to selectively form a polyimide mask (against anodization). This mask may be provided in a place where a contact is formed later or a place where a wiring is divided. (The polyimide mask is not shown in the figure.)

Then, anodic oxidation is performed. Dissolve tartaric acid in ethylene glycol, 1-5%, for example 3%
PH of the solution prepared by adding ammonia solution.
Was set to about 7. Then, using the platinum mesh electrode as the cathode and the substrate 10 as the anode, an electric current was passed through the wiring 24 to start anodization.

Initially, the voltage is 3 to 6 V / min, for example 4 V / min.
The current is passed so that the voltage rises in minutes, and the voltage is
When the voltage reached 250 V, for example 220 V, the voltage increase was stopped, the voltage was kept constant, and the state was maintained until the current reached 20 μA / cm ² . As a result, thickness 1500-
3000Å, for example 2000Å aluminum oxide 25
Was formed. The existing portion of the polyimide mask (not shown) was not anodized due to the masking effect. The time required for anodization was 40 to 70 minutes, typically 55 minutes. (Fig. 2 (A))

Next, the photoresist mask 26 was patterned except for the island-shaped silicon regions 22. The patterning shape at this time is as shown in FIG.
The one shown in (C) was adopted. That is, in the portion where the step of the silicon region 22 and the gate electrode 24 intersect,
The structure is such that it is not doped.

The gate insulating film 23 in such a step portion is formed.
Since the covering property is poor and thin, defects such as pinholes frequently occur, parasitic TFTs are generated along the step portion, and the leak current caused thereby becomes a problem. By adopting such a doping pattern, since the step portion does not become a part of the TFT, it is possible to significantly reduce the leak current and the like.

Then, using this mask, impurities (phosphorus or boron) were implanted into the silicon region 22 by the plasma doping method. When phosphorus is injected, phosphine (PH ₃ ) is used as the doping gas, and the acceleration voltage may be 65 to 100 kV, for example 80 kV.
In the case of implanting boron, diborane (B ₂ H ₆ ) is used as a doping gas and the acceleration voltage is 50 to 80 k.
It may be V, for example, 65 kV. Dose amount is 1 × 10
^{It is set to 15 to} 5 × 10 ¹⁵ cm ^-2 , for example, 3 × 10 ¹⁵ cm ^-2 . Thus, the impurity region 27 is self-aligned with the gate electrode portion (gate electrode 24 and anodic oxide 25).
a and 27b were formed. The impurity region and the gate electrode 24 are in a state (offset state) separated by a distance Y in the horizontal direction. (Fig. 2 (B))

Next, using this mask 26, a part of the silicon oxide film 23 was etched. After the etching process was completed, the mask 26 was removed. When the pattern of the mask 26 is also exposed in a portion other than the semiconductor region 22 as shown in FIG. 3A, the underlying silicon oxide film is etched as in Example 1 (X in FIG. 1D). However, when the exposed portion is limited to only the semiconductor region 22 as shown in FIG. 3C, such a problem did not occur. T after etching the gate insulating film 23 according to each pattern
The state of FT is shown in FIGS. 3 (B) and (D). Figure 2
FIG. 3C shows a cross section of the TFT shown in FIG.
Remarkably, at this time, the anodic oxide (aluminum oxide) 25 is also etched and set back by the distance Z, so that the boundaries of the impurity regions are exposed. (Fig. 2 (C))

Further, the implanted impurities were activated by the laser annealing method. In this process,
The boundary between the impurity regions was also irradiated with laser light and was sufficiently activated. The laser used was a KrF excimer laser (wavelength 248 nm, pulse width 20 nse.
In c), the energy density on the irradiated surface is 250 to 400 m.
J / cm ² , for example, 300 mJ / cm ² . At the time of laser irradiation, the substrate is heated to 200 to 400 ° C., for example 300
It may be heated to ° C.

Subsequently, a silicon oxide film 28 having a thickness of 5000 to 8000 Å, for example 5000 Å, is formed as an interlayer insulator by the plasma CVD method, and further, an indium tin oxide film having a thickness of 500 to 1500 Å, for example 800 Å ( An ITO) film was deposited and patterned to form a pixel electrode (ITO) 29.
Further, contact holes were formed in the interlayer insulator 28, and wirings 30a and 30b were formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. And
0.1 to 1 atm, 250 to 400 ° C., for example, 1 atm, 3
Annealing was performed in a hydrogen atmosphere at 50 ° C. for 30 to 120 minutes, for example, 30 minutes. The semiconductor circuit is completed through the above steps. (Fig. 2 (D))

[Embodiment 3] FIG. 4 shows a cross-sectional view of a manufacturing process of this embodiment. An underlayer film 41 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 40 by sputtering. Further, an amorphous silicon film having a thickness of 200 to 2000 Å, for example 1500 Å, was deposited by the plasma CVD method. Subsequently, the thickness is 200 to 1000Å, for example, 20 by the sputtering method.
A 0Å silicon oxide film was deposited as a protective film. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 42P and 42N.

Next, a thickness of 80 is obtained by the sputtering method.
A silicon oxide film 43 having a thickness of 0 to 1500 Å, for example 1000 Å, is deposited as a gate insulating film, and subsequently, a thickness of 3000 to 6000 Å, for example, 60 is formed by a sputtering method.
00Å aluminum film (containing 1-5% silicon)
Was deposited. In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film is patterned to form the gate electrode 44P,
44N is formed, and the surface thereof is made to have a thickness of 1500 to 3000 Å, for example 2000 by the anodizing method as in the second embodiment.
It was coated with Å anodic oxide (aluminum oxide) 45P and 45N. (Fig. 4 (A))

Next, only the semiconductor region 42N was exposed, and the other portion was masked with the photoresist 46N. And
Impurities (phosphorus) were implanted into the silicon region 42N by the plasma doping method using the photoresist mask 46N and the gate electrode portion (gate electrode 44N and anodic oxide 45N) as masks. The doping pattern is shown in Figure 3.
The shape shown in FIG. Phosphine (PH ₃ ) was used as the doping gas, and the acceleration voltage was set to 65
˜110 kV, for example 80 kV. 1 x dose
It was set to 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, the N-type impurity region 47N was formed. After the doping was completed, a part of the silicon oxide film 43 was etched using the mask 46N. (Fig. 4 (B))

Further, this time, only the semiconductor region 42P is exposed, the other portion is masked by the photoresist 46P, and the silicon region 42 is formed by the plasma doping method.
Impurities (boron) were injected into P. Also in this case, the doping pattern has a shape as shown in FIG. Diborane (B ₂ H ₆ ) was used as a doping gas, and the acceleration voltage was set to 50 to 80 kV, for example, 65 kV. The dose amount was set to 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, a P-type impurity region 47P was formed. Mask 46P after doping is completed
Part of the silicon oxide film 43 was etched by using.
(Fig. 4 (C))

After that, the introduced impurities were activated by laser irradiation. Kr for laser
An F excimer laser (wavelength 248 nm) was used,
In addition, XeF excimer laser (wavelength 353 nm),
XeCl excimer laser (wavelength 308 nm), Ar
You may use F excimer laser (wavelength 193nm) etc. Laser energy density is 250-400m
The irradiation was performed at J / cm ² , for example, 280 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one location.

After activation of the impurities, a thickness of 5000
~ 8000 Å, for example 6000 Å silicon oxide film 48 as an interlayer insulator TEOS (tetra ethoxy silane,
Si (OC ₂ H ₅ ) ₄ ) is used as a raw material to form a plasma CVD method, and a contact hole is formed in the plasma CVD method.
Wirings 49a, 49b, 49c and 49d were formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. Then, in a hydrogen atmosphere at 0.1 to 1 atmosphere and 250 to 400 ° C., for example, 0.1 atmosphere and 350 ° C., 30 to 120 atmosphere.
Annealing was performed for 30 minutes, for example. Through the above steps, a CMOS semiconductor circuit is completed. (Fig. 4
(D))

[0033]

According to the present invention, it is possible to improve the yield of TFTs, enhance their reliability, and bring out the maximum characteristics. Moreover, in obtaining such a large effect, there is a great merit that it can be carried out without involving a large process change, investment, and technological development. Although the present invention has been described by taking the TFT on the insulating substrate as an example,
Needless to say, the present invention can be applied to a TFT formed on a single crystal semiconductor substrate. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views illustrating a manufacturing process of a TFT of Example 1.

2A to 2C show cross-sectional views of a manufacturing process of a TFT of Example 2.

FIG. 3 shows a doping pattern and the like of the TFT of Example 2.

4A to 4C show cross-sectional views of a manufacturing process of a TFT of Example 3.

FIG. 5 is a cross-sectional view of a manufacturing process of a conventional TFT.

FIG. 6 is a cross-sectional view of a manufacturing process of a conventional TFT.

[Explanation of symbols]

10 ... Substrate (Corning 7059) 11 ... Base insulating film (silicon oxide) 12 ... Island semiconductor region (silicon) 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode (silicon) ) 15 ... Mask (photoresist) 16 ... Impurity region (source, drain) 17 ... Interlayer insulator (silicon oxide) 18 ... Source electrode, drain electrode (titanium nitride / aluminum) 20 ... Substrate (Corning 7059) 21 ... Base insulating film (silicon oxide) 22 ... Island semiconductor region (silicon) 23 ... Gate insulating film (silicon oxide) 24 ... Gate electrode (aluminum) 25. ..Anodic oxide (aluminum oxide) 26 ... Mask (photoresist) 27 ... Impurity region (source, drain) 28 ... Interlayer insulator (silicon oxide) ) 29 ... pixel electrode (ITO) 30 ... source electrode, the drain electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 21/266 21/265 21/324 Z 8617-4M 8617-4M H01L 21/265 G

Claims (4)

[Claims] 1. A first step of forming an island-shaped thin film semiconductor region, a second step of forming an insulating film to cover the semiconductor region, and a gate electrode portion formed across the semiconductor region. And a fourth step of providing a mask by exposing at least a part of the gate electrode portion and the semiconductor region.
Step, a fifth step of irradiating the doping impurity ions at a high speed, a sixth step of selectively removing the insulating coating using the mask, and a seventh step of irradiating a laser or equivalent strong light. And a method of manufacturing a thin film transistor. 2. The method of manufacturing a thin film transistor according to claim 1, wherein in the gate electrode portion, the surface of the gate electrode formed of a conductive material is covered with an oxide of the conductive material. 3. The method for manufacturing a thin film transistor according to claim 1, wherein the material forming the gate electrode portion is a material containing aluminum as a main component. 4. The method for manufacturing a thin film transistor according to claim 1, wherein the sixth step is performed by wet etching using a solution containing hydrofluoric acid.