JPH0496157A - Main memory data protective circuit - Google Patents

Abstract

PURPOSE:To prevent system down occurring due to the destruction of a program or data by detecting whether or not access from a bus master to main memory is the one to allocated memory space. CONSTITUTION:A main memory data protective circuit 3 decides whether or not the access of a processor 5 and the bus master 6 to the main memory 1 is valid based on an address on an address bus 100 and bus use permission signals 110-114 from a bus controller 4 to the processor 5 and the bus master 6. A memory controller 2 is informed of a decision result by an output signal 102. The memory controller 2 controls read/write on the main memory 1 by the access from the processor 5 and the bus master 6 corresponding to the signal 102, and when the access from the processor 5 and the bus master 6 to the main memory 1 is invalid, the memory controller 2 neglects invalid access. Thereby, it is possible to prevent the system down occurring due to the destruction of the program and the data.

Description

Detailed Description of the Invention Technical Field The present invention relates to a main memory data protection circuit, and more particularly to data protection in the main memory of an information processing device where the main memory is read from and written to by a plurality of bus masters connected to a common bus. .

Conventional technology Conventionally, in this type of information processing device, when the main memory can be accessed by multiple bus masters, the memory space of the main memory is divided, the divided memory space is allocated to each bus master, and the allocation The main memory was controlled only by software, such as by creating a program according to the instructions.

In such conventional information processing devices, if a bus master writes to a memory space allocated to another bus master in the main memory due to a malfunction of the device or an error in programming, the memory space will be lost. The disadvantage is that stored programs and data are destroyed, leading to system failure.

Another disadvantage is that if the corruption of the program or data is not discovered, processing will continue according to the incorrect program or data, leading to system malfunction.

Furthermore, since it is generally difficult to discover the bus master that has destroyed programs or data, there is a drawback that resolution of problems caused by program or data destruction is delayed.

Purpose of the Invention The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional system.It can prevent system failures due to destruction of programs and data, and can easily identify equipment failures and program errors. The purpose is to provide a main memory data protection circuit that can be discovered.

Composition of the Invention A main memory data protection circuit according to the present invention is a main memory data protection circuit for an information processing device having a main memory accessible by a plurality of bus masters connected to a common bus, wherein address information holding means for holding address information for specifying an allocated memory space; and holding bus master information for specifying a bus master that can access the memory space specified by the address information of the address information holding means. address comparison means for comparing an address on the common bus with address information in the address information holding means; and bus use permission information indicating a bus master using the common bus and the bus master information holding means. The present invention is characterized in that it includes a bus master comparing means for comparing bus master information of the address comparing means and the bus master comparing means, and a control means for controlling access to the main memory according to the comparison results of the address comparing means and the bus master comparing means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, a main memory 1 is connected to a processor 5-h (h-1) connected to an address bus [00 and a data bus 101] under the control of a memory controller 2.
, 2, ...) and bus master 6-i (i-1, 2
, 3, . . . ), reading and writing are performed in response to accesses from Note that the bus master 6-4 uses DMA (
Main memory 1 by direct memory access) transfer
Read and write to.

The main memory data protection circuit 3 receives addresses on the address bus 100 and data from the bus controller 4 to the processor 5-.
h and bus use permission signal 11j to bus master 6-i.
(j-0, 1, 2, 3, 4, ...), it is determined whether the access to the main memory 1 by the processor 5-h and the bus master 6-i is valid or not, and the determination result is The memory controller 2 is notified by the output signal 102.

Memory controller 2 is main memory data protection circuit 3
The main memory 1 is accessed by the processor 5-h and the bus master 6-i in response to the output signal 102 from the main memory 1.
Control reading and writing to.

That is, if access to main memory 1 from processor 5-h and bus master 6-1 is unauthorized, memory controller 2 ignores the unauthorized access and prevents main memory 1 from destroying programs and data.

FIG. 2 is a block diagram showing the configuration of the main memory data protection circuit 3 of FIG. 1. In the figure, register 30-
In addition, 3l-k (k-1, 2, . . . -) holds address information indicating memory spaces allocated to the processor 5-h and the bus master 6-1, respectively, in the main memory 1. That is, the register 30-k holds the start address of the memory space, and the register 31-k holds the end address of the memory space.

The comparator circuits 32- and 33- compare the address on the address bus 10a with the address information held in the register 30- and 31-k, and the address on the address bus 100 or the register 30- is set to 31-k. - detects whether or not it is within the memory space indicated by the address information.

The register 34-k holds data indicating the type of bus master that can access the memory space designated by the address information in the register 30- and 31-.

The OR gate 35- takes the logical sum of the outputs of the comparator circuit 32- and 33-, and outputs the result to the enable terminal of the tri-state driver 36-.

The tri-state driver 36- sends data indicating the type of bus master held in the register 34-k to the OR gate 37-j.

The OR gate 37-j performs the logical sum of the bus use permission signal 11j from the bus controller 4 to the processor 5-h and bus master 6-i and the output signal to the tri-state driver 36-, and stores the result as main memory data. It is output to the memory controller 2 as an output signal 102-j of the protection circuit 3.

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

First, the processor 5-1 writes the start address of the memory space into the register 30-k and the end address of the memory space into the register 31-k of the main memristor protection circuit 3 via the address bus 100 and the data bus 101, respectively. It will be done. That is, registers 30- and 31- can be used as a pair to indicate one memory space.

Further, the processor 5-1 writes data indicating the type of bus master that can access the memory space specified by the address information in the register 30- and the register 31- in the register 34-k.

The respective outputs are input to the register 34- from the top of FIG. Bit 1. ...and bit 0. Bit 1.
If the value of .

Generally, the types of processor 5-h and bus master 6-i connected to bus use permission signal 11j are determined for each system configuration.

The processor 5-h and bus master 6-i send addresses to the address bus 10 to access the main memory 1.
When the address is output to 0, this address is compared with the value in the register 30- by the comparator circuit 32-, and if the address is greater than or equal to the value in the register 30-, the output to the comparator circuit 32- becomes active low. .

Further, the address output to the address bus 100 is compared with the value in the register 31- by the comparison circuit 33-, and if the address is less than the value in the register 31-, the output to the comparison circuit 33- is activated. become low.

For example, assuming that only processor 5-1 and bus master 6-1 may access the memory space specified by the value of register 30-1.31-1, bits 0. Only bit 2 is set to "1" and the other bits are set to "0".

Here, the processor 5-2 registers 30-1 31-
When a memory space designated by a value of 1 is accessed, the outputs of comparison circuits 32-1 and 33-1 both become low, and the output of OR gate 35-1 also becomes low.

As a result, the tristate driver 36-1 drives the contents of the register 34-1 to the register 37-j.

At this time, since the processor 5-2 is using the address bus 100 and the data bus 101, only the bus use permission signal 111 of the bus use permission signals 11j is low.

Further, since bit 1 of the register 34-1 is set to "0", both inputs of the OR gate 37-2 become low, and only the output signal 102-2 of the output signals 102-j becomes low.

This output signal 102-2 causes the memory controller 2 to indicate that even though the memory space specified by the value of the register 30-1.31-1 has not been allocated to the processor 5-2, the processor 5-2 The processor 5-2 determines that an attempt is made to illegally access the space.
Ignore access from.

On the other hand, when the processor 5-1 and the bus master 6-1 access the memory space, the processor 37-j
All of the output signals 102-j from the memory controller 2 become inactive high, and the memory controller 2 determines that there is no unauthorized access and accepts the access from the processor 5-1 and the bus master 6-1.

That is, by sampling the output signal 102-j from the main memory data protection circuit 3 at appropriate points, the memory controller 2 detects unauthorized access to unallocated memory space and the device attempting the unauthorized access. Can be detected.

In this way, processor 5-h and bus master 6-i
The comparison circuits 32- and 33- determine whether the access is to the main memory 1 or the allocated memory space.
If a memory space allocated to a certain bus mask or another bus master in main memory 1 is accessed due to a device failure or programming error, However, since it is possible to detect such unauthorized access and notify the memory controller 2, it is possible to prevent the destruction of programs and data in the main memory 1 due to such unauthorized access, and the system down due to the destruction of programs and data. I can do something.

Furthermore, since it is possible to determine which bus master has made the unauthorized access based on the output signal 102-j from the oracle 37-j, it is possible to easily discover failures in the device or errors in the program.

As described in detail, according to the present invention, by detecting whether or not an access from a bus master to main memory is an access to an allocated memory space, system downtime due to program or data destruction can be prevented. This has the effect of making it possible to easily discover failures in devices and errors in programs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the main memory adapter protection circuit of FIG. 1. Explanation of symbols of main parts 1...Main memory 2...Memory controller 3...Main memory data protection circuit 4...
- Bus controller 5-1. 5-2...Processors 6-1 to 6-3...Bus master 30-1.30-2.31-1.31-2゜34-1.
34-2...Register 32-1.32-2 33-1.33-2...Comparison circuit 35-1.3
5-2゜37-1~37-4...Or Gate 36-1.3
6-2... Tri-state driver applicant NEC Corporation (1 other person)

Claims (1)

[Claims] (1) A main memory data protection circuit for an information processing device having a main memory accessible by a plurality of bus masters connected to a common bus, the circuit for specifying a memory space allocated to the bus master in the main memory. address information holding means for holding address information; bus master information holding means for holding bus master information specifying a bus master that can access the memory space specified by the address information of the address information holding means; address comparison means for comparing the above address with address information in the address information holding means; and bus master comparison means for comparing bus use permission information indicating a bus master using the common bus with bus master information in the bus master information holding means. and a control means for controlling access to the main memory according to the comparison results of the address comparison means and the bus master comparison means.