JPH0487659U - - Google Patents
Info
- Publication number
- JPH0487659U JPH0487659U JP13079890U JP13079890U JPH0487659U JP H0487659 U JPH0487659 U JP H0487659U JP 13079890 U JP13079890 U JP 13079890U JP 13079890 U JP13079890 U JP 13079890U JP H0487659 U JPH0487659 U JP H0487659U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- metal base
- gnd line
- circuit pattern
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 3
- 239000002131 composite material Substances 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
第１図は本考案の一実施例の縦断面図、第２図
はそれの金属ベース回路基板の平面図、第３図は
その切断側面図、第４図は従来装置の縦断面図、
第５図はそれの金属ベース回路基板の斜視図、第
６図はその切断側面図である。
２……金属板、３……絶縁層、５〜７……電子
部品、９……外装ケース、１３……金属ベース回
路基板、１４……導電性接着剤。
Fig. 1 is a longitudinal sectional view of an embodiment of the present invention, Fig. 2 is a plan view of its metal base circuit board, Fig. 3 is a cut side view thereof, and Fig. 4 is a longitudinal sectional view of a conventional device.
FIG. 5 is a perspective view of the metal base circuit board thereof, and FIG. 6 is a cutaway side view thereof. 2... Metal plate, 3... Insulating layer, 5-7... Electronic components, 9... Exterior case, 13... Metal base circuit board, 14... Conductive adhesive.
Claims (1)
上に導体で回路パターンを形成してなる金属ベー
ス回路基板を備え、この金属ベース回路基板の前
記回路パターン上に、半導体素子を含む各電子部
品を搭載し、これらの各電子部品を、前記金属ベ
ース回路基板の周端面に外嵌固着した外装ケース
で覆つた複合型半導体装置において、前記回路パ
ターンにおけるＧＮＤラインの端部を前記金属ベ
ース回路基板の端部まで延設し、このＧＮＤライ
ンの端部と前記金属板の端面とを、これらに付着
した導電性接着剤により電気的接続したことを特
徴とする複合型半導体装置。 A metal base circuit board is provided, in which an insulating layer is formed on one surface of a metal plate, and a circuit pattern is formed with a conductor on the insulating layer, and each circuit including a semiconductor element is placed on the circuit pattern of the metal base circuit board. In a composite semiconductor device in which electronic components are mounted and each of these electronic components is covered with an exterior case that is externally fitted and fixed to the peripheral end surface of the metal base circuit board, the end of the GND line in the circuit pattern is connected to the metal base. 1. A composite semiconductor device, characterized in that the GND line extends to an end of a circuit board, and the end of the GND line and the end face of the metal plate are electrically connected by a conductive adhesive adhered thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13079890U JPH0487659U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13079890U JPH0487659U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0487659U true JPH0487659U (en) | 1992-07-30 |
Family
ID=31878113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13079890U Pending JPH0487659U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0487659U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017005170A (en) * | 2015-06-12 | 2017-01-05 | 富士電機株式会社 | Semiconductor device |
-
1990
- 1990-11-30 JP JP13079890U patent/JPH0487659U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017005170A (en) * | 2015-06-12 | 2017-01-05 | 富士電機株式会社 | Semiconductor device |