JPH0479147B2 - - Google Patents
Info
- Publication number
- JPH0479147B2 JPH0479147B2 JP58089521A JP8952183A JPH0479147B2 JP H0479147 B2 JPH0479147 B2 JP H0479147B2 JP 58089521 A JP58089521 A JP 58089521A JP 8952183 A JP8952183 A JP 8952183A JP H0479147 B2 JPH0479147 B2 JP H0479147B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- region
- conductivity type
- impurity concentration
- gto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 95
- 239000012535 impurity Substances 0.000 claims description 30
- 238000009792 diffusion process Methods 0.000 description 22
- 239000000758 substrate Substances 0.000 description 16
- 239000010931 gold Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000000691 measurement method Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 235000007516 Chrysanthemum Nutrition 0.000 description 1
- 244000189548 Chrysanthemum x morifolium Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はゲートターンオフサイリスタ（以下
GTOと略称する）に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a gate turn-off thyristor (hereinafter referred to as
(abbreviated as GTO).
一般にGTOはゲート電極に正及び負のパルス
を印加することにより、ターンオン及びターンオ
フを可能とするため、転流回路が不要であり、且
つ小型軽量にできる。またスイツチング時間が著
しく小さいので高周波で動作できるという利点を
有しているものである。
In general, GTOs can be turned on and off by applying positive and negative pulses to the gate electrode, so a commutation circuit is not required and the GTO can be made smaller and lighter. Furthermore, since the switching time is extremely short, it has the advantage of being able to operate at high frequencies.
この種のGTOの一般構造として第１図に示す
るものがある。 The general structure of this type of GTO is shown in Figure 1.
１は半導体基板、２はＮ型のベース領域（NB
層）である第１半導体領域で、キヤリアライフタ
イムを小さくするために金（Au）等のライフタ
イムキラーが拡散されている。３は上記半導体基
板１の他主面に拡散等により形成され、第１半導
体領域２と隣接し、かつ第１半導体領域２とＰ−
Ｎ接合（J1）を形成するＰ型のアノード領域（PE
層）である第２半導体領域、４は上記半導体基板
１の一主面に拡散等により形成され、第１半導体
領域２と隣接し、かつ第１半導体領域２とＰ−Ｎ
接合（J2）を形成するＰ型のベース領域（PB層）
である第３半導体領域、５はこの第３半導体領域
の一主面に選択的に、例えば平面形状が菊形ある
いは櫛形等の形状に形成され、上記第３半導体領
域４とＰ−Ｎ接合（J3）を形成するＮ形のカソー
ド領域（NE層）である第４半導体領域、６は上
記半導体基板１の他主面上に形成され、上記第２
半導体領域３と電気的に接続されるアノード電
極、７は上記半導体基板１の一主面上に選択的に
形成され、上記第３半導体領域４と電気的に接続
されるゲート電極、８は上記半導体基板１の一主
面上に選択的に形成され、上記第４半導体領域と
電気的に接続されるカソード電極である。 1 is a semiconductor substrate, 2 is an N-type base region (N B
A lifetime killer such as gold (Au) is diffused in the first semiconductor region, which is a layer (layer), to reduce the carrier lifetime. 3 is formed by diffusion or the like on the other main surface of the semiconductor substrate 1, is adjacent to the first semiconductor region 2, and is in contact with the first semiconductor region 2 and P-
A P - type anode region (P E
A second semiconductor region 4, which is a layer), is formed on one main surface of the semiconductor substrate 1 by diffusion or the like, is adjacent to the first semiconductor region 2, and has a P-N relationship with the first semiconductor region 2.
P-type base region (P B layer) forming the junction (J 2 )
A third semiconductor region, 5, is selectively formed on one main surface of the third semiconductor region, for example, in a planar shape of a chrysanthemum shape or a comb shape, and forms a P-N junction ( A fourth semiconductor region 6, which is an N-type cathode region (N E layer) forming the semiconductor substrate 1, is formed on the other main surface of the semiconductor substrate 1, and is formed on the second main surface of the semiconductor substrate 1.
An anode electrode 7 electrically connected to the semiconductor region 3, a gate electrode 7 selectively formed on one main surface of the semiconductor substrate 1 and electrically connected to the third semiconductor region 4, and 8 a gate electrode electrically connected to the third semiconductor region 4; This is a cathode electrode that is selectively formed on one main surface of the semiconductor substrate 1 and electrically connected to the fourth semiconductor region.
このように構成されたGTOの従来例の一例と
して、次のような拡散プロフアイル等を有したも
のがある。 As an example of a conventional GTO configured in this manner, there is one having the following diffusion profile.
半導体基板１の厚さが340μｍ、第１半導体領
域２の不純物濃度が１×1014個／cm3、第２半導体
領域３の不純物濃度及び拡散深さがそれぞれ１×
1018個／cm3、55〜65μｍ、第３半導体領域４の不
純物濃度及び拡散深さがそれぞれ１×1018個／
cm3、55〜65μｍ、第４半導体領域５の不純物濃
度、及び拡散深さがそれぞれ６×1021個／cm3、17
〜23μｍ、第１半導体領域２と第４半導体領域５
との間における第３半導体領域４の幅、つまり第
４半導体領域５直下の第３半導体領域４の厚さＬ
（以下PB幅と称す。）が40〜50μｍ、第４半導体領
域５と第３半導体領域４の拡散プロフアイルの
Ｗ・Ｐ（Working Point）が２〜９×1017個／cm3、
金の拡散量が１〜２×1013個／cm3である。 The thickness of the semiconductor substrate 1 is 340 μm, the impurity concentration of the first semiconductor region 2 is 1×10 14 /cm 3 , and the impurity concentration and diffusion depth of the second semiconductor region 3 are each 1×.
10 18 pieces/cm 3 , 55 to 65 μm, and the impurity concentration and diffusion depth of the third semiconductor region 4 are each 1×10 18 pieces/cm 3 .
cm 3 , 55 to 65 μm, the impurity concentration of the fourth semiconductor region 5 and the diffusion depth are 6×10 21 particles/cm 3 , 17, respectively.
~23 μm, first semiconductor region 2 and fourth semiconductor region 5
The width of the third semiconductor region 4 between the
(hereinafter referred to as P B width) is 40 to 50 μm, W·P (Working Point) of the diffusion profile of the fourth semiconductor region 5 and the third semiconductor region 4 is 2 to 9×10 17 pieces/cm 3 ,
The amount of gold diffused is 1 to 2×10 13 pieces/cm 3 .
なお、Ｗ・Ｐとは、２種の半導体ドナ不純物と
アクセプタ不純物がほぼ同数となる領域をさし、
２種のＰ、Ｎ半導体の疑似領域である。 Note that W・P refers to a region where two types of semiconductor donor impurities and acceptor impurities are approximately equal in number,
These are pseudo regions of two types of P and N semiconductors.
このような拡散プロフアイルを有したGTOに
おいては、上記Ｗ・Ｐが２〜９×1017個／cm3と小
さく、第３半導体領域４の不純物濃度１×1018
個／cm3と低いため、カソード電極８からの電子の
注入が第３半導体領域４内で再結合されるのが少
なく、第２半導体領域３へと注入されるため、
GTOを小さなゲートトリガ電流Igtで瞬時にター
ンオンさせることができるものである。 In a GTO having such a diffusion profile, the above W·P is as small as 2 to 9×10 17 pieces/cm 3 , and the impurity concentration of the third semiconductor region 4 is 1×10 18
Since the number of electrons/cm 3 is low, electrons injected from the cathode electrode 8 are less likely to be recombined within the third semiconductor region 4 and are injected into the second semiconductor region 3.
The GTO can be turned on instantly with a small gate trigger current I gt .
しかるに、第３半導体領域４の不純物濃度が小
さいため、繰り返しターンオフできる最大の電流
値（ITGQ、以下最大ターンオフ電流と称す。）が
小さく、200AクラスのGTOとしては不向きであ
つた。つまり、第３半導体領域４の不純物濃度が
小さいため、第３半導体領域４の抵抗が大きく、
ゲート電極７へ電流が引き抜けず、局部的な電流
集中により素子の熱破壊が生じる。 However, since the impurity concentration of the third semiconductor region 4 is low, the maximum current value ( ITGQ , hereinafter referred to as maximum turn-off current) that can be repeatedly turned off is small, making it unsuitable for a 200A class GTO. In other words, since the impurity concentration of the third semiconductor region 4 is low, the resistance of the third semiconductor region 4 is high;
Current cannot be drawn to the gate electrode 7, and thermal breakdown of the device occurs due to local current concentration.
一方、最大ターンオフ電流ITGQを強くする方法
として最大ターンオフ電流ITGQが第３半導体領域
４の不純物濃度と比例関係にあることを利用し
て、単に第３半導体領域４の不純物濃度を大きく
する方法も考えられるが、ゲートトリガ電流Igt
が大きくなり、電力損失が大きくなるものであ
る。また最悪の場合には第４半導体領域５、第３
半導体領域４、及び第１半導体領域２の三層をト
ランジスタで見た時の電流増幅係数α〔NPN〕が
低下して、GTOサイリスタが動作しなくなる場
合が多々生じた。 On the other hand, as a method of increasing the maximum turn-off current I TGQ , there is a method of simply increasing the impurity concentration of the third semiconductor region 4 by utilizing the fact that the maximum turn-off current I TGQ is in a proportional relationship with the impurity concentration of the third semiconductor region 4. is also possible, but the gate trigger current I gt
becomes large, and power loss becomes large. Furthermore, in the worst case, the fourth semiconductor region 5, the third
There were many cases where the current amplification coefficient α [NPN] when looking at the three layers of the semiconductor region 4 and the first semiconductor region 2 as a transistor decreased and the GTO thyristor stopped operating.
この発明は上記した諸事情に鑑みてなされたも
のであり、Ｐ形アノード層上にＮ形ベース層、Ｐ
形ベース層を順次積層し、該Ｐ形ベース層表面に
選択的にＮ形カソード領域を形成してなる半導体
層構造を有するゲートターンオフサイリスタにお
いて、Ｎ形カソード領域直下のＰ形ベース層の厚
さＬを50＜Ｌ≦60μｍとし、かつワーキング・ポ
イントの不純物濃度を1.0〜2.5×1018個／cm3に設
定することにより、最大ターンオフ電流が大き
く、かつゲートリガ電流が小さいゲートターンオ
フサイリスタタを提供するものである。
This invention was made in view of the above-mentioned circumstances, and includes an N-type base layer and a P-type anode layer on a P-type anode layer.
In a gate turn-off thyristor having a semiconductor layer structure in which type base layers are sequentially laminated and an N type cathode region is selectively formed on the surface of the P type base layer, the thickness of the P type base layer directly under the N type cathode region By setting L to 50<L≦60μm and setting the impurity concentration at the working point to 1.0 to 2.5×10 18 pieces/cm 3 , we provide a gate turn-off thyristator with a large maximum turn-off current and a small gate trigger current. It is something to do.
以下にこの発明の実施例を説明する。 Examples of the present invention will be described below.
第１図に示した構成のGTOにおいて、ゲート
トリガ電流が小さく、最大ターンオフ電流が大き
いものを得るために種々の拡散プロフアイルを有
するGTOを製造し、実験を行なつた結果、ベー
ス領域となる第１半導体領域２とカソード領域と
なる第４半導体領域５との間におけるベース領域
となる第３半導体領域４の幅（PB幅）と第３半
導体領域４と第４半導体領域５からなる拡散プロ
フアイルのＷ・Ｐとを調整することにより、最大
ターンオフ電流ITGQが非常に大きく、ゲートトリ
ガ電流が小さく、かつ制御よく安定的に製造でき
るGTOが得られることが判明した。 In the GTO with the configuration shown in Figure 1, in order to obtain a GTO with a small gate trigger current and a large maximum turn-off current, we fabricated GTOs with various diffusion profiles and conducted experiments. The width (P B width) of the third semiconductor region 4 which becomes the base region between the first semiconductor region 2 and the fourth semiconductor region 5 which becomes the cathode region and the diffusion made up of the third semiconductor region 4 and the fourth semiconductor region 5 It has been found that by adjusting the profile W and P, a GTO can be obtained that has a very large maximum turn-off current ITGQ , a small gate trigger current, and can be manufactured stably with good control.
この実験結果から得られたGTOの拡散プロフ
アイル等の一例は次のようなものである。 An example of the GTO diffusion profile obtained from this experimental result is as follows.
半導体基板として12mm角程度であり、厚さが
330〜340μｍ、第１半導体領域２の不純物濃度が
１×1014個／cm3、第２半導体領域３の不純物濃度
及び拡散深さがそれぞれ４×1018個／cm3、60〜
70μｍ、第３半導体領域４の不純物濃度及び拡散
深さがそれぞれ４×1018個／cm3、60〜70μｍ、第
４半導体領域５の不純物濃度、拡散深さ、幅、及
び長さがそれぞれ６×1021個／cm3、17〜23μｍ、
150〜300μｍ、1.5〜4.0mm、PB幅Ｌが50〜60μｍ、
第３半導体領域４と第４半導体領域５からなる拡
散プロフアイルのＷ・Ｐが1.0〜2.5×1018個／cm3
金の拡散量が１〜２×1013個／cm3である。 As a semiconductor substrate, it is approximately 12mm square and thick.
330 to 340 μm, the impurity concentration of the first semiconductor region 2 is 1×10 14 /cm 3 , and the impurity concentration and diffusion depth of the second semiconductor region 3 are 4×10 18 /cm 3 , 60 to 60, respectively.
70 μm, the impurity concentration and diffusion depth of the third semiconductor region 4 are respectively 4×10 18 particles/cm 3 and 60 to 70 μm, and the impurity concentration, diffusion depth, width, and length of the fourth semiconductor region 5 are respectively 6 ×10 21 pieces/ cm3 , 17~23μm,
150-300μm, 1.5-4.0mm, P B width L is 50-60μm,
W/P of the diffusion profile consisting of the third semiconductor region 4 and the fourth semiconductor region 5 is 1.0 to 2.5×10 18 pieces/cm 3
The amount of gold diffused is 1 to 2×10 13 pieces/cm 3 .
なお、第４半導体領域５が第３半導体領域４を
取り囲む構造になつているものであり、200〜
300AクラスのGTOである。また第４半導体領域
５の電極面積は20〜50mm2と非常に小さくて良いも
のである。 Note that the fourth semiconductor region 5 has a structure surrounding the third semiconductor region 4, and
It is a 300A class GTO. Further, the electrode area of the fourth semiconductor region 5 may be as small as 20 to 50 mm 2 .
さらに、このGTOにおける、第４半導体領域
５の表面から深さ方向における拡張プロフアイル
は第２図に示すようになつているものである。第
２図において曲線ＡはRS測定法により実際に測
定した第４半導体領域５における深さ方向への不
純物濃度を示し、曲線ＢはRS測定法により実際
に測定した第３半導体領域４のPB幅における深
さ方向への不純物濃度を示し、点線Ｃは第３半導
体領域４における表面からの深さ方向への不純物
濃度の一部を示し、曲線Ｄは第１半導体領域２に
おける深さ方向の不純物濃度を示すものであり、
曲線Ａと点線Ｃとの交点が第３半導体領域４と第
４半導体領域５からなる拡散プロフアイルのＷ・
Ｐになるものである。なお、RS測定法とは広が
り抵抗測定とも言われ、半導体基板を３〜5°に研
磨し、針を当てながら抵抗値を測定するものであ
り、この測定値をＸ−Ｙレコーダにて記録するも
のである。 Further, in this GTO, the extended profile in the depth direction from the surface of the fourth semiconductor region 5 is as shown in FIG. In FIG. 2, curve A shows the impurity concentration in the depth direction in the fourth semiconductor region 5 actually measured by the R S measurement method, and curve B shows the impurity concentration in the third semiconductor region 4 actually measured by the R S measurement method. The dotted line C shows a part of the impurity concentration in the depth direction from the surface in the third semiconductor region 4, and the curve D shows the impurity concentration in the depth direction in the P B width. It indicates the impurity concentration in the direction,
The intersection of the curve A and the dotted line C is W of the diffusion profile consisting of the third semiconductor region 4 and the fourth semiconductor region 5.
It becomes P. The R S measurement method is also called spread resistance measurement, and involves polishing the semiconductor substrate to 3 to 5 degrees and measuring the resistance value while applying a needle to the surface.This measurement value is recorded with an X-Y recorder. It is something to do.
このようにして得られたGTO第３図に白丸で
示す分布のものは、最大ターンオフ電流ITGQが
400A以上であり、上記従来例のものの２〜３倍
の値を示し、200AクラスのGTOとして遮断容量
が約２倍程度の保障が必要であり、この点をも充
分満足するものであつた。しかも、ゲートトリガ
電流Igtも250〜500ｍＡと小さいものであつた。 The distribution of the GTO obtained in this way, shown in white circles in Figure 3, has a maximum turn-off current I TGQ .
The current was 400A or more, which was two to three times the value of the conventional example, and as a 200A class GTO, it was necessary to guarantee about twice the breaking capacity, and this point was also fully satisfied. Furthermore, the gate trigger current I gt was as small as 250 to 500 mA.
次に、上記で得られたGTOの製造方法につい
て第１図を用いて説明する。まずＮ型ベース領域
となる第１半導体領域２が構成される不純物濃度
が１×1014／cm3であるシリコンからなる半導体基
板１を用意する。その後この半導体基板の両主面
にGa拡散でもつてＰ型ベース領域となる第３半
導体領域４とＰ型アノード領域となる第２半導体
領域３を形成する。この時第２、第３半導体領域
３，４ともに不純物濃度が４×1018個／cm3、拡散
深さが60〜70μｍになるように制御される。その
後、半導体基板１の一主面上に１〜2μｍの厚さ
の熱酸化膜を形成し、写真製製版技術によつて第
３半導体領域４表面の酸化膜を選択的に窓をあ
け、その後この第３半導体領域４内にリン等で拡
散して、Ｎ型カソード領域となる第４半導体領域
５を形成する。この時第４半導体領域は幅が150
〜300μｍ、長さが1.5〜4.0mmであり、第３半導体
領域４が取り囲む構造であり、不純物濃度が６×
1021個／cm3、拡散深さが17〜23μｍで、かつPB幅
Ｌが50〜60μｍになるように制御される。その
後、半導体基板の他主面側から、850℃、10分間、
金を拡散する。この時の第３半導体領域４におけ
る金の拡散量は１〜２×1013個／cm3となる。次に
第３半導体領域４からゲート電極７を、第２半導
体領域３からアノード電極６を、第４半導体領域
５からカソード電極８をそれぞれ取り出す。その
後、アノード電極６の上にパツケージの電極を取
りつけ、又カソード電極８、ゲート電極７からは
例えばAlワイヤーなどをボンデイングしてパツケ
ージの電極と接続して完成させるものである。 Next, a method for manufacturing the GTO obtained above will be explained using FIG. 1. First, a semiconductor substrate 1 made of silicon having an impurity concentration of 1×10 14 /cm 3 in which a first semiconductor region 2 serving as an N-type base region is formed is prepared. Thereafter, a third semiconductor region 4 which becomes a P-type base region and a second semiconductor region 3 which becomes a P-type anode region are formed by Ga diffusion on both main surfaces of this semiconductor substrate. At this time, the impurity concentration in both the second and third semiconductor regions 3 and 4 is controlled to be 4×10 18 particles/cm 3 and the diffusion depth is controlled to be 60 to 70 μm. Thereafter, a thermal oxide film with a thickness of 1 to 2 μm is formed on one main surface of the semiconductor substrate 1, and windows are selectively opened in the oxide film on the surface of the third semiconductor region 4 by photolithography. Phosphorus or the like is diffused into this third semiconductor region 4 to form a fourth semiconductor region 5 which becomes an N-type cathode region. At this time, the width of the fourth semiconductor region is 150
~300μm, length 1.5~4.0mm, surrounded by third semiconductor region 4, impurity concentration 6×
10 21 pieces/cm 3 , the diffusion depth is 17 to 23 μm, and the P B width L is controlled to be 50 to 60 μm. Then, from the other main surface side of the semiconductor substrate, heat at 850℃ for 10 minutes.
Spread the money. At this time, the amount of gold diffused in the third semiconductor region 4 is 1 to 2×10 13 pieces/cm 3 . Next, the gate electrode 7 is taken out from the third semiconductor region 4, the anode electrode 6 is taken out from the second semiconductor region 3, and the cathode electrode 8 is taken out from the fourth semiconductor region 5. Thereafter, the electrode of the package is attached onto the anode electrode 6, and the cathode electrode 8 and gate electrode 7 are bonded with, for example, Al wires to connect to the electrodes of the package to complete the structure.
なお、上記したPB幅Ｌが50〜60μｍであり、第
３半導体領域４と第４半導体領域５とからの拡散
プロフアイルのＷ・Ｐが１〜2.5×1018個／cm3で
ある実施例のGTOと比較するため、上記Ｗ・Ｐ
を２〜９×1017個／cm3と下げたGTO（第３図に黒
丸で示す分布のもの）を製造したところ、最大タ
ーンオフ電流ITGQは200A未満と小さく素子が破壊
してしまい、さらに上記条件のもとにPB幅Ｌを
70〜80μｍ程度に広げても同様であつた。また、
上記Ｗ・Ｐを３〜４×1018個／cm3と高くした
GTOを製造したところ、最大ターンオフ電流ITGQ
は非常に強くなつたものの、ゲートトリガ電流
Igtが大きくなりすぎ、GTOそのものが動作しな
くなり、さらに上記条件のもとにPB幅Ｌを50μｍ
より浅くしても同様であつた。つまり、上記した
PB幅Ｌが50〜60μｍ、Ｗ・Ｐが１〜2.5×1018個以
外のものは、GTOの電気特性から判断して充分
満足する特性が得られなかつたものである。 Note that the P B width L described above is 50 to 60 μm, and the diffusion profile W/P from the third semiconductor region 4 and the fourth semiconductor region 5 is 1 to 2.5×10 18 particles/cm 3 . In order to compare with the example GTO, the above W.P.
When we manufactured a GTO with a lower value of 2 to 9 × 10 17 pieces/cm 3 (with the distribution shown by the black circles in Figure 3), the maximum turn-off current I TGQ was less than 200 A, resulting in device destruction. Under the above conditions, P B width L is
The same result was obtained even when the film was expanded to about 70 to 80 μm. Also,
The above W/P was increased to 3~4×10 18 pieces/cm 3
When GTO is manufactured, the maximum turn-off current I TGQ
Although the gate trigger current has become very strong,
I gt becomes too large, the GTO itself stops working, and under the above conditions, the P B width L is reduced to 50 μm.
The same result was obtained even if the depth was made shallower. In other words, the above
Those with a P B width L of 50 to 60 μm and a W·P of 1 to 2.5×10 18 are those in which sufficiently satisfactory characteristics were not obtained judging from the electrical characteristics of the GTO.
なお上記実施例では第４半導体領域５をＮ型不
純物を選択的に拡散したものとしたが、第３半導
体領域４全面にＮ型不純物を拡散して形成後、選
択エツチングによりマルチエミツタ構造にしても
のでも良く、これを連結した構造にしたものとし
ても良いものである。またAu拡散の効果を利用
しないで、アノードシヨート構造のものでも良
い。 In the above embodiment, the fourth semiconductor region 5 is formed by selectively diffusing N-type impurities, but it is also possible to form a multi-emitter structure by selectively etching the N-type impurities over the entire surface of the third semiconductor region 4. However, it is also possible to have a structure in which these are connected. Alternatively, it may be of an anode short structure without utilizing the effect of Au diffusion.
この発明は以上述べたように、Ｐ形アノード層
上にＮ形ベース層、Ｐ形ベース層を順次積層し、
該Ｐ形ベース層表面に選択的にＮ形カソード領域
を形成してなる半導体層構造を有するゲートター
ンオフサイリスタにおいて、Ｎ形カソード領域直
下のＰ形ベース層の厚さＬを50＜Ｌ≦60μｍと
し、かつワーキング・ポイントの不純物濃度を
1.0〜2.5×1018個／cm3に設定したので、最大ター
ンオフ電流を400A以上と大きく増大でき、かつ
ゲートトリガ電流を250〜500ｍＡと小さく抑える
ことができる効果がある。
As described above, this invention sequentially laminates an N-type base layer and a P-type base layer on a P-type anode layer,
In the gate turn-off thyristor having a semiconductor layer structure in which an N-type cathode region is selectively formed on the surface of the P-type base layer, the thickness L of the P-type base layer directly below the N-type cathode region is 50<L≦60 μm. , and the impurity concentration at the working point is
Since it is set to 1.0 to 2.5×10 18 pieces/cm 3 , the maximum turn-off current can be greatly increased to 400 A or more, and the gate trigger current can be suppressed to a small value of 250 to 500 mA.
また、このように不純物濃度を1.0〜2.5×1018
個／cm3に設定したとき、最大ターンオフ電流を増
大できるが、このとき特にターンオフ時間のバラ
ツキに対しては、カソード領域を幅150〜300ミク
ロン、長さ1.5〜4.0ミリメートルとしてこの間に
おいて不純物濃度を上記のようにすることによ
り、ターンオフ時間のバラツキを押えて最大ター
ンオフ電流の制御性を良くすることができる。 Also, in this way, the impurity concentration is 1.0 to 2.5 × 10 18
The maximum turn-off current can be increased when the current is set to 150 to 300 microns in width and 1.5 to 4.0 millimeters in length, especially for variations in turn-off time . By doing as described above, it is possible to suppress variations in the turn-off time and improve the controllability of the maximum turn-off current.
第１図はGTOの一般的内部構造を示す断面図、
第２図はこの発明の一実施例であるGTOの拡散
プロフアイルを示した図、第３図はこの発明の実
施例と比較例におけるPB幅とＷ・Ｐ値によるITGQ
の分布を示す図である。
図において、１は半導体基板、２は第１半導体
領域（Ｎ形ベース層）、３は第２半導体領域（Ｐ
形アノード層）、４は第３半導体領域（Ｐ形ベー
ス層）、５は第４半導体領域（Ｎ形カソード領
域）、６はアノード電極、７はゲート電極、８は
カソード電極である。
Figure 1 is a sectional view showing the general internal structure of the GTO.
Fig. 2 is a diagram showing the diffusion profile of GTO, which is an embodiment of the present invention, and Fig. 3 is a diagram showing the I TGQ according to the P B width and W/P value in the embodiment of the present invention and the comparative example.
FIG. In the figure, 1 is a semiconductor substrate, 2 is a first semiconductor region (N-type base layer), and 3 is a second semiconductor region (P
4 is a third semiconductor region (P-type base layer), 5 is a fourth semiconductor region (N-type cathode region), 6 is an anode electrode, 7 is a gate electrode, and 8 is a cathode electrode.
Claims (1)
層、第２導電形ベース層を順次積層し、該第２導
電形ベース層表面に選択的に第１導電形カソード
領域を形成してなる半導体層構造を有するゲート
ターンオフサイリスタにおいて、 上記第２導電形ベース層の、第１導電形カソー
ド領域直下の部分の厚さＬを50＜Ｌ≦60μｍと
し、 かつ第１導電形ベース層及び第２導電形カソー
ド領域の幅150〜300ミクロン、長さ1.5〜4.0ミリ
メートルからなる間の、両導電形不純物の濃度が
同数となる領域を、1.0〜2.5×1018個／cm3の不純
物濃度を有する領域としたことを特徴とするゲー
トターンオフサイリスタ。[Claims] 1. A first conductivity type base layer and a second conductivity type base layer are sequentially laminated on a second conductivity type anode layer, and a first conductivity type cathode is selectively formed on the surface of the second conductivity type base layer. In a gate turn-off thyristor having a semiconductor layer structure formed by forming a region, a thickness L of a portion of the second conductivity type base layer immediately below the first conductivity type cathode region is 50<L≦60 μm, and the first conductivity type base layer Between the conductivity type base layer and the second conductivity type cathode region, which have a width of 150 to 300 microns and a length of 1.5 to 4.0 mm, a region where the concentration of both conductivity type impurities is the same is 1.0 to 2.5 × 10 18 pieces/cm. A gate turn-off thyristor characterized in that the region has an impurity concentration of 3 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8952183A JPS59214261A (en) | 1983-05-20 | 1983-05-20 | Gate turn-off thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8952183A JPS59214261A (en) | 1983-05-20 | 1983-05-20 | Gate turn-off thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59214261A JPS59214261A (en) | 1984-12-04 |
| JPH0479147B2 true JPH0479147B2 (en) | 1992-12-15 |
Family
ID=13973101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8952183A Granted JPS59214261A (en) | 1983-05-20 | 1983-05-20 | Gate turn-off thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59214261A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5413313A (en) * | 1977-07-01 | 1979-01-31 | Gen Corp | Method of processing digital signal |
| JPS5438777A (en) * | 1977-09-01 | 1979-03-23 | Toshiba Corp | Semiconductor device |
| JPS5651868A (en) * | 1979-10-05 | 1981-05-09 | Nec Corp | Semiconductor device |
| JPS5812359A (en) * | 1981-07-14 | 1983-01-24 | Mitsubishi Electric Corp | Semiconductor device |
-
1983
- 1983-05-20 JP JP8952183A patent/JPS59214261A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5413313A (en) * | 1977-07-01 | 1979-01-31 | Gen Corp | Method of processing digital signal |
| JPS5438777A (en) * | 1977-09-01 | 1979-03-23 | Toshiba Corp | Semiconductor device |
| JPS5651868A (en) * | 1979-10-05 | 1981-05-09 | Nec Corp | Semiconductor device |
| JPS5812359A (en) * | 1981-07-14 | 1983-01-24 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59214261A (en) | 1984-12-04 |
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