JPH0475385A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device wherein the thicknesses or the heights of both electric plates can be made accurately equal by using a metallic layer containing at least Ti or Cr as a electric charge material, depositing the layer on the surface of a crystal, and forming an electrode. CONSTITUTION:An InP layer 2, an In0.53Ga0.47As layer 3 and an InP layer 4 are formed on an InP substrate 1. Zn is diffused from a surface 4' of the layer 4, and a P-type region 5 is formed. Then, a hole 6 (depth is 6.5mum) is formed from the surface 4' by selective etching. An insulating film 9 is deposited on the side surface of a central mesa 7. Thereafter, electrode metals 10 and 10' are deposited. The compositions of the electrodes 10 and 10' are made to be Ti (0.1mum), Pt (0.3mum), Au (lmum) and Sn (0.5mum). The electrode 10 is formed only on the surface of the P-type region 5. The electrode 10' is formed along the side surfaces of mesas 8 and 8' connecting the surface 4' of the crystal layer 4 and the exposed part of the substrate 1 at the bottom surface of the hole 6. Then, the electrodes are bonded to a wiring board 14 by a face-down method. As a result, the semiconductor device characterized by excellent manufacturing yield rate and the excellent performance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides crystal compositions of Inl-xGaxAs□-yP
The present invention relates to a compound semiconductor device represented by y and a method for manufacturing the same.

[Conventional technology]

In an ohmic electrode in a semiconductor device, the n-type part and the n-type part are usually made of different materials, and different steps are required to form each part. For this reason, the manufacturing process is complicated;
This was an obstacle to reducing manufacturing costs and improving yield. Particularly in devices where the height or thickness of the electrodes on both sides must be exactly the same, this is difficult to control, which causes a significant drop in yield.

When the crystal base material is Ga□-zAQxAs-based, using AuGe-based metal as the electrode material makes a good ohmic electrode for the n-type part and the n-type part, and it is possible to form the electrodes simultaneously in one process. , Special Publication Showa 54-13348
is shown. however.

In order to obtain ohmic characteristics with the above electrode, it is necessary to cause an alloying reaction between the crystal base material and the metal layer through sophisticated control. Furthermore, the above alloying treatment introduces defects and stress into the crystal base material, and there is a drawback that an active region such as a pn junction cannot be provided in the immediate vicinity of the electrode forming portion. In addition, the same material has a forbidden band width of 1.4 eV or less In, -
In xGaxAst-yPy, the system containing a large amount of InP had the drawback of not exhibiting good ohmic properties. Therefore, in the above crystal system, the n-type part contains A u G e system,
For the p-type part, different materials are used, such as Ti-containing systems such as Ti-Au.

[Problem to be solved by the invention]

In the conventional technology, the base material is I nl-xGaxAs, -yP
y (1≧x≧0, 1≧y≧0), forbidden band width 1.4eV
An ohmic electrode material that can be used commonly for the following p- and n-type crystals has not been disclosed.

The present invention provides a method that simplifies the electrode formation process by providing a material that can be used commonly as an ohmic electrode for both Pen crystals, and allows the thickness and 4i height of both templates to be exactly the same. Our goal is to provide semiconductor devices that can be used in a variety of applications.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as an electrode material,
A metal layer containing at least Ti or Cr, i.e., Ti
, Au, TiPt, TiPd.

Conventionally, the above materials are
B) is known as a material for the P-type part, but it has been found that good characteristics can also be obtained for the N-type part. As a result, if this material is used, ohmic electrodes can be formed in both the Pen regions in the same process.

[Effect]

Since an ohmic characteristic force of 1 is obtained for the p- and n-type surface regions, the electrodes can be formed in the same process, which simplifies the process and allows both electrodes to have the same thickness or height.

[Example] Example 1 An embodiment of the present invention will be described with reference to FIG.

The crystal shown in FIG. 4(a) was used. In the figure, 1 is an InP substrate (4X 10" an-3: n-type), 2 to 4 are layers fabricated by vapor phase epitaxy, and 2 is an InP (I
"ai-', n type, 2 μm thick), 3 is In, 53
G a(,,47A s (I X 10"an-3,
N type.

2 μm thick), 4 is I n P (I x 10” an-
3, n-type.

Zn was diffused from the surface 4' of the 0 layer 4, which had a thickness of 2 .mu.m) to form a p-type region 5 (depth 2.2 .mu.m, diameter 50 .mu.m).

Then by selective etching from surface 4'.

66 (depth 6.5 μm) shown in FIG. 6(b) was formed.

Here, 7 is a central mesa with a diameter of 30 μm, 8 and 8'
is a rectangular peripheral mesa with a length of 200 μm and a width of 50 μm, and the interval between 8 and 8' is 100 μm.First, after depositing an insulating film 9 on the side surface of the central mesa 7, electrode metal 10 and 10' was applied. The composition of the electrodes 10 and 10' is T i (0-1 um) s from the side closer to the crystal.
Pt (0-3pm) -Au (1μm),
5n (0.5 μm). Here, the electrode 10 was formed only on the surface of the p-type region 5, and the electrode 10' was formed over the side surfaces of mesas 8, 8' connecting the surface 4' of the crystal layer 4 and the exposed portion of the substrate 1 on the bottom surface of the 66.

Next, as shown in FIG. 3(c), the electrodes were bonded to the wiring board 14 by a face-down method. The wiring board 14 has an insulating film 12 and Au layers 11 and 11' arranged on the surface of a semi-insulating InP 13. The Au layers 11 and 11' match the electrodes 10 and 10' in shape, and the other It also has lead parts that connect each part to other circuits or wiring bonding parts (not shown in the figure). The conditions for face-down bonding are a temperature of 360°C.

After bonding, a voltage was applied from the lead portion of the wiring board 14, and the characteristics were examined. As a result, it was found that the series resistance of the electrode determined from the forward voltage-current characteristics was 2Ω, and that the electrode 10' with respect to the n-type portion was good. Also, when applied in the opposite direction, this device has a L value of 1.3 μm infrared light.
It operated as a good light receiving device with A/W sensitivity. The production yield in this example was 98%. Similar effects can be obtained by using TiAu, TiPd, CrPt instead of the TiPt part.
.

It was also obtained with CuAu and CrPd. Conventional method, ie, the electrode 10 for the n-type region 5 is the same as above, but the electrode 10' for the n-type region is AuGe-Ni-Au.
When -8n was used, the production yield was 55%. The main cause of the failure was poor bonding to the wiring board due to a difference in the thickness of the picture electrode.

Embodiment 2 FIG. 2 is a sectional view showing the manufacturing process of a junction type FET according to another embodiment of the present invention. In the same figure (a), semi-insulating In
On the P substrate 20, an n-InP active layer (thickness approximately 0.5 μm, impurity concentration I
-3) and n-I n, , 3G a@, 47A S0
*14P6h@6 (thickness approximately 0.3pm, impurity concentration I
A cap 22 (X 10"an-3) was provided. Furthermore, a SiO2 film 23 with a thickness of about 2,000 layers was deposited on the crystal surface. In order to selectively diffuse Zn, a SiO2 film 23 was deposited on the crystal surface. The diffusion mask window 24 (window width 1 μm) is made of Si○ using photoresist processing technology and dry etching technology.
2 film 23 has a striped opening 24 with a groove width of about 0.7 μm.
has been established.

Next, Zn was selectively diffused into the striped portion 24 to form a p-type layer 25 of a desired depth, thereby forming a p-type junction gate.

Next, as shown in FIG. 2(b), openings 26 and 27 were formed in the 5in2 film in the portions corresponding to the source and drain using a photoresist processing technique. After removing the resist film, Cr (approximately 200 layers) and Pt were deposited at a substrate temperature of 300° C. so that the deposited metal was incident perpendicularly to the wafer surface.
(about 2000 people).

Au (approximately 3,000 layers) was sequentially vacuum-deposited.

Next, the SiO2 film 23 is etched using an HF-based etching solution.
By etching and removing unnecessary parts of metal (C
r-Pt-A'u) was lifted off and removed, and electrodes (source, drain) were patterned.

Next, the wafer was heat-treated at 400° C. for about 1 minute to sink the source, gate, and drain electrodes.

Finally, as shown in FIG. 2(c), the source electrode 31.
Gate electrode 30. The periphery of the element portion including the drain electrode 32 was selectively chemically etched using a photoresist processing technique to form an isolation mesa 33.

In the junction FET shown in this embodiment, the source, gate, and drain electrodes can each be formed using the same laminated metal material, and the manufacturing process can be simplified. Furthermore, since the source, gate, and drain electrodes are completely on the same plane, face-down mounting on microwave printed circuit board circuits and the like is easy, and the device exhibits excellent high-frequency characteristics.

Furthermore, in this embodiment, since the fine ohmic electrode to the junction gate layer 25 can be formed in a self-aligned manner, the fine ohmic electrode 30 for gate can be manufactured extremely easily.

In this example, Cr-Pt-A is used as the metal material of the electrode.
Although the example using u was explained, Cr-Au.

Cr-Pd-Au etc. can also be used.

〔Effect of the invention〕

As is clear from the description of the embodiments above, according to the present invention, it is possible to overcome the difficulties of the conventional techniques related to electrode formation and bonding, and it is possible to manufacture semiconductor devices with high manufacturing yield and high performance. It becomes possible.

[Brief explanation of drawings]

FIGS. 1 and 2 are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 1- n -I n P substrate, 5 ・p-type Zn diffusion layer,
20... Semi-insulating InP substrate, 30... Gate electrode, 31... Source electrode, 32... Drain electrode.・( Agent Patent Attorney Katsuma Ogawa (, = ″( Figure ■ (!ri

Claims (1)

[Claims] 1. Main composition is In_1_-_xGaxAs_1_-_y
P_y (1≧x≧0, 1≧y≧0), forbidden band width 1.4
1. A semiconductor device comprising a metal layer containing Ti or Cr formed on the surface of each of two p-type and n-type regions having a voltage of eV or less. 2. The metal layer is at least Ti-Au, Ti-Pt, T
2. The semiconductor device according to claim 1, comprising a stacked layer or an alloy containing any one of i-Pd, Cr-Au, Cr-Pt, and Cr-Pd. 3. Formation of a metal layer containing Ti or Cr is performed using p-type and n-type In_1_-_xGaxAs_1_-_yP_y
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on the regions at the same time. 4. At least part of the surface on which the metal layer containing Ti or Cr is formed has an impurity concentration of 10^1^8 cm^-^
2. The semiconductor device according to claim 1, wherein the number is 3 or more.