JPS62102566A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a series resistance and a leakage conductance by composing a gate protection diode of an N-type layer formed on a semi-insulating compound semiconductor substrate, and a P<+> type layer with a contact of the N-type layer and an insulating film layer as an end face. CONSTITUTION:Part of an N-type layer 2 region formed on a semi-insulating semiconductor substrate 1 is removed, an insulating film 5 is formed on the removed region, and a P<+> type thin film 6 of a gate protection diode is formed on the layer 2 with the contact of the layer 2 with the layer 5 as an end face. A P-type side electrode 10 which bridges over the part of the layer 6 and the insulating film is formed to form a P<+>-N junction diode. Thus, the accuracy of photoetching step of the P-type side electrode contacting hole is alleviated to prevent the yield from decreasing and to reduce a series resistance and a leakage conductance.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device including a protection element, particularly a semiconductor device including a protection diode having a p4-n junction structure provided on a semi-insulating compound semiconductor substrate. Regarding equipment.

(Prior Art) An n-channel GaAs MESFET exhibits excellent low noise characteristics in a high frequency region, and is widely used in consumer equipment such as microwave band communication equipment and television tuners.

For example, when this device is used in a television chainer, a gate protection element is usually provided between the Schottky gate and the source in order to ensure the electrical surge resistance necessary for the television component. As a protection element, a p+-n junction diode structure is generally adopted, except when the protection element is forward biased, such as the second gate of a dual-gate FET.

(Problems to be Solved by the Invention) Problems in the structure and manufacturing process of a p+-n junction diode formed by thermal diffusion, ion implantation, etc. as a current protection diode will be described below.

The gate protection diode is GaAs MESF
Since it is provided on the input side of the ET, the electrical characteristics of the protection diode are strongly related to the high frequency performance (especially noise characteristics) of the FET. Figures 2 (a), (b), and (c) respectively show the junction capacitance (Cz) and leakage conductance (Gz) when the equivalent circuit of the protection diode is viewed as shown in Figure 3.
), which shows how the series resistance (Rz) affects the noise figure of the FET. It can be seen that reducing the junction capacitance (Cz), leakage conductance (Gz), and series resistance (R,z) is essential for improving the noise figure. but,
The lower limit of the junction capacitance, that is, the junction area, is more limited than the desired surge resistance, and cannot be reduced unnecessarily. Therefore, it becomes necessary to reduce series resistance and leakage conductance.

FIGS. 4(a) and 4(b) are a plan view and a sectional view of a Brenner type p+-n junction gate protection diode formed by thermal diffusion, ion implantation, or the like. In FIG. 4(b), an n-type source region 22 is provided on a semi-insulating GaAs substrate 21 by ion implantation of Sl, and a p+ layer 23 is further formed in a part of the source region 22 by ion implantation. . Next, an insulating film 24 is deposited on the entire surface, and windows are formed on the source region 22 and the p+ layer 23. After that, a source electrode 25 and a wiring electrode 26 are formed on the source region 22.
A p-side electrode 27 and a wiring electrode 28 are formed on the p+ layer 23.

Normally, in order to reduce the series resistance without increasing the junction area, the dimensional structure of a p''-11 diode is such that the long side (4) is long and the short side (te) is short, as shown in Figure 4 (6). However, the short side (/!,) is limited by the accuracy of the photoetching process for the contact hole of the p++ pole 23. For example, when designing with W=100 μm!=10 μm, the p++ contact hole Even if holes can be formed by a photoetching process with an accuracy of ±2 μm,
Contact area S (=w'Xl')≦96μm×6μm
As a result, the series resistance of the p+ electrode conc 21 portion increases. If an attempt is made to obtain a larger contact area, contact between the p" electrode 23 and the 0 layer 22 tends to occur, leading to an increase in leakage conductance.

Furthermore, as shown in the cross-sectional view of FIG. 5, a p+-n junction diode structure in which a p+ layer 23' is formed over a part of the 0 layer 22 and the semi-insulating substrate 21 is also possible. Dual gate structure p+-n diode)
When used as a gate protection diode for MESFET, the first
There is a disadvantage that the withstand voltage of the second gate varies depending on the bias state of the gate.

The present invention eliminates the above-mentioned drawbacks, and is capable of reducing yield loss in the photo-etching process, reducing series resistance and leakage conductance without increasing junction capacitance, and achieving excellent Sarno resistance and low noise. The present invention provides a protection diode structure for manufacturing FETs with gate protection diodes at a high yield.

(Means for Solving the Problems) A compound semiconductor device according to the present invention includes an n-type layer formed on a semi-insulating compound semiconductor substrate, and a region formed on a region from which a part of this n-type layer is removed. An insulating film, a p+ layer formed on the n-type layer with the contact point between the n-type layer and the insulating film layer as an end surface, and a p-side electrode formed over a part of the p+ layer and the insulating film layer. It is characterized by using a p+-〇 junction diode as a gate protection diode.

(Function) In the present invention, a part of the n-type layer region provided on the semi-insulating semiconductor substrate is removed, an insulating film is formed on the removed region, and the n-type layer and the insulating film layer are separated. n with the contact point as the end face
Form a p+ thin layer of gate protection diode-1' on the mold layer. By forming a p-side electrode that extends over a portion of this p+ layer and the insulating film to form a p''-11 junction diode, the accuracy of the photoetching process for the p-side electrode contact hole is eased and yield reduction is reduced. At the same time, the series resistance and leakage conductance are reduced.Also, since the insulating film layer is sandwiched between the semi-insulating substrate and the p-side electrode metal, the @1 gate and the second gate of the FET are This p+-n diode can be
It is intended to be used as a gate protection diode for ET.

(Example) Examples of the present invention will be described below with reference to the drawings.

In FIG. 1, n is placed on a semi-insulating GaAs substrate 1.
The type active layer (n = 1.5 x 10 "cm-") 2 has a thickness of 0.15 μm, and the n-type source region 3 and drain region (both n = 5 x 10 "am-") 4 have a thickness of 0.6 μm.
It was formed by Si ion implantation to a thickness of . Then, a part of the source 113 is removed by mesa etching to a thickness of about 0.6 μm, and an insulating film 5 is deposited to a thickness of about 0.5 μm.

100 μm x 10 μm of the insulating film on the source region 3 including the etched edge of the 0 layer is removed, a window is opened on the region that should become the p+ layer, and a p layer is formed by ion implantation or Zn thermal diffusion.
+ layer (p≧10"co+-co) 6 was formed to a thickness of 0.1 μm. After that, source and drain ohmic electrodes 7 were formed.
. Second gate electrodes 9, 9 are formed. At the same time, a p-side electrode "O" is formed on the p+ layer 6, and a wiring metal T
iAu11 was formed thereon to fabricate a GaAs MESFET with a gate protection diode.

In the present invention, contact between the p+ layer 6 and the p-side electrode 10 is allowed up to the mesa-etched end surface, so if the p-side contact hole 12 is formed in a photoetching process with an accuracy of ±2 μm, the contact area of the p-side electrode 10 can be reduced. S≦96μI11×8
μm, and the series resistance of the gate protection diode can be reduced. In addition, the increase in leakage coefficient due to contact between the 1] side electrode 10 and the n-type layer 3 due to an error in the photoetching process for forming the p-side contact hole is reduced, and the noise of the FET with a gate protection diode is reduced, and the yield is also improved. Improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of an FET with a gate protection diode according to an embodiment of the present invention. Figure 2 (a), (b), and (c) show the equivalent circuit parameters of the gate protection diode and the F with gate protection diode.
It is a figure explaining the correlation with the noise figure of ET. FIG. 3 is a diagram showing an equivalent circuit of a p+-〇 structure gate protection diode. FIGS. 4(a) and 4(b) are a plan view and a cross-sectional view, respectively, of a gate protection diode having a general planar structure. Figure 5 shows a p
FIG. 3 is a cross-sectional view of a p + -n junction diode with a + layer; DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... N-type active layer, 3... Source region, 4... Drain region, 5... Insulating film, 6... P+ layer, 7...・Source electrode, end...drain electrode, 9...1st. Second gate electrode, 10... p+ ohmic contact Tlk, 11...
・Wiring electrode, 12...p (ill contact hole. Patent applicant: Sharp Co., Ltd. agent)
People Patent Attorneys Previously Two Idiots Figure 1 Yasuiri〉 (Yukiya Monument ¥)〉 Castle

Claims (1)

[Claims] (1) An n-type layer formed on a semi-insulating compound semiconductor substrate, an insulating film formed on a region where a part of this n-type layer is removed, and a contact point between the n-type layer and the insulating film layer at the end surface. The p^+-n layer consists of a p^+ layer formed on the n-type layer as
A compound semiconductor device characterized in that a junction diode is used as a gate protection diode.