JPH0474466A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the time required for manufacturing an MIS type semiconductor and, at the same time, to reduce the number of required processes by the number of processes required for making a diffusion layer for controlling the threshold voltage of the semiconductor device by combining the process for diffusing an impurity for controlling the threshold voltage and another process for diffusing an impurity for forming source and drain diffusion layers to one process. CONSTITUTION:After a gate oxide film 2, polysilicon gate electrodes 3, and an oxide film 4 are successively formed on a silicon substrate 1, a photoresist mask 5 for forming gate electrodes is formed and the film 4 and electrodes 3 are etched. Then the oxide film 4 left on the electrodes 3 are alternately etched by using a photoresist mask 6 for writing a program. Thereafter, an impurity for controlling the threshold voltage of an MIS type semiconductor device is diffused into a channel section below the electrode 3 and n-type ions 7 are implanted for diffusing an impurity for forming source and drain diffusion layers so as to form a diffusion layer 8a for controlling the threshold voltage and source and drain diffusion layers 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a MIS type semiconductor device for read-only memory.

The threshold voltage of a conventional MIS type semiconductor device can be controlled by the type and concentration of impurity diffusion in a semiconductor substrate that becomes a channel. Information stored in a read-only memory device is selectively stored depending on whether the transistor operating threshold voltage under the gate is positive or negative with respect to a reference voltage. This conventional example will be explained with reference to FIG. Figure 2 (a) to (d)
(This is a cross-sectional view of the manufacturing process of an MIS type semiconductor device.)
, for example, as shown in FIG. 2(a), a silicon substrate 1
A photoresist mask 11 for isolating the n-type diffusion region is placed on the
is formed, and n-type ions 12 are implanted using this photoresist mask 11 to selectively diffuse the n-type impurity to form a threshold voltage control diffusion layer 13. Next, as shown in FIG. 2(b), after forming a gate oxide film 2 and a gate electrode polysilicon 3, a photoresist mask 5 for forming a gate electrode is formed.
form. Next, as shown in FIG. 2(C), the gate electrode polysilicon 3 is removed using the photoresist mask 5 as a mask.
After etching, n-type ions 14 are implanted to diffuse the n-type impurity to form source and drain diffusion layers 15. In this case, as shown in FIG. 2(d), a source diffusion layer and a drain diffusion layer at both ends sandwiching a plurality of gate electrodes arranged in series (only the right end is shown in the figure),
In reality, the aluminum wiring 10 is connected only to the left end (also located at the left end) via the interlayer insulating film 9. Therefore, no wiring is formed in the source/drain equivalent diffusion region 15a corresponding to each of the plurality of gate electrodes between the diffusion layer in which the aluminum wiring 10 is formed and the drain diffusion layer.

The memory cell formed as described above generally has a structure called a single-layer polysilicon NAND type multi-gate. Since this structure has one contact for multiple gate electrodes, it is advantageous for highly integrated circuits, so it has been widely used in memory cell structures of large-capacity read-only memory devices in recent years. It has the advantage of high integration.

Problems to be Solved by the Invention In such a conventional method of manufacturing an MIS type semiconductor device,
It has two disadvantages. One is that it takes a long time from the read-only memory programming process to completion to form the threshold voltage control diffusion layer 13 before and after the formation of the Goo 4, and the other is that the threshold voltage control diffusion layer 13 is formed. This increases the number of steps and increases the cost of the semiconductor device.

The present invention solves the above-mentioned problems, and aims to provide a low-cost, large-capacity MIS type semiconductor device that takes a short time from the programming process to completion of a read-only memory.

Means for Solving the Problems In order to achieve the above objects, the present invention provides a step of diffusing impurities for controlling the threshold voltage of an MIS type semiconductor device and a step of diffusing impurities for forming a source diffusion layer and a drain diffusion layer. is combined into one process.

Effect of the Invention With the above-described configuration, the present invention can shorten the period from the programming process to completion of the read-only memory, and the number of steps can be reduced by not forming a threshold voltage control diffusion layer.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

As shown in FIG. 1(a'), after forming a gate oxide film 2, a gate electrode polysilicon 3, and an oxide film 4 on a silicon substrate 1, a photoresist mask 5 for forming a gate electrode is used.
An oxide film 4. is formed as shown in FIG. 1(b). Gate electrode polysilicon 3 is etched. Next, the oxide film 4 remaining on the gate electrode polysilicon 3 is etched every other time using the photoresist mask 6 for program writing and gradation as a mask. Next, as shown in FIG. 1(C), impurities for controlling the threshold voltage of the MIS type semiconductor device are diffused into the channel portion under the gate electrode 3, and impurities for forming the source diffusion layer and the drain diffusion layer are also diffused. N-type ions 7 are implanted for diffusion to form a threshold voltage control diffusion layer 8a.
and form a source and train diffusion layer 8b. The accelerating voltage for ion implantation at this time is set to such a condition that the ions do not penetrate through the oxide film 4 and the ions penetrate through the gate electrode polysilicon 3. Next, as shown in FIG. 1(ω), an interlayer insulating film 9 and an aluminum wiring 10 are formed. In this case, similarly to the conventional example, as shown in FIG. 1(d), the source diffusion layer and the drain diffusion layer at both ends sandwiching a plurality of gate electrodes arranged in series (only the right end is shown in the figure). However, in reality, the aluminum wiring 10 is connected only to the wire (which is actually located further to the left). Therefore, no wiring is formed in the source/drain equivalent diffusion layer corresponding to each of the plurality of gate electrodes between the source diffusion layer and the drain diffusion layer to which the aluminum wiring 10 is connected.

Effects of the Invention As is clear from the above embodiments, according to the present invention, the impurity diffusion layer for controlling the threshold voltage and the impurity diffusion layers for the source and drain are formed by a single ion implantation. The period from the programming process to completion can be shortened, and a large-capacity MIS type semiconductor device can be provided while keeping the cost low.

[Brief explanation of drawings]

1(a) to 1(d) are step-by-step cross-sectional views of a method for manufacturing an MIS type semiconductor device according to an embodiment of the present invention, and FIG. 2(a)
) to (d) are step-by-step cross-sectional views in a conventional method for manufacturing a semiconductor device. 1...Silicon substrate (semiconductor substrate), 2...
...Gate oxide film (gate insulating film), 3...
Gate electrode polysilicon (gate electrode), 4...
・Oxide film, 7...n-type ions (ion implantation),
8a... Diffusion layer for threshold voltage control, 8b...
...Source and drain diffusion layers.

Claims (1)

[Claims] MIS in which a source diffusion layer and a drain diffusion layer are formed on the surface of a semiconductor substrate, and a plurality of gate electrodes arranged in series are formed on the surface of the semiconductor substrate between the source diffusion layer and the drain diffusion layer with a gate insulating film interposed therebetween. In a method for manufacturing a type semiconductor device, an oxide film is laminated on a gate electrode on a region where impurities are not diffused, and an impurity for controlling a threshold voltage is applied to a channel portion below the oxide film through the plurality of gate electrodes arranged in series. a source diffusion layer corresponding to each of the source diffusion layer, the drain diffusion layer, and the plurality of gate electrodes;
A method for manufacturing an MIS type semiconductor device, characterized in that a highly concentrated impurity is diffused into a drain equivalent diffusion layer by a single ion implantation.