JPH0472423B2 - - Google Patents

Info

Publication number
JPH0472423B2
JPH0472423B2 JP57099704A JP9970482A JPH0472423B2 JP H0472423 B2 JPH0472423 B2 JP H0472423B2 JP 57099704 A JP57099704 A JP 57099704A JP 9970482 A JP9970482 A JP 9970482A JP H0472423 B2 JPH0472423 B2 JP H0472423B2
Authority
JP
Japan
Prior art keywords
state
frame
pulse
output
hunting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57099704A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58215841A (ja
Inventor
Botaro Hirosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57099704A priority Critical patent/JPS58215841A/ja
Priority to US06/501,729 priority patent/US4541104A/en
Priority to CA000430005A priority patent/CA1195007A/en
Priority to DE8383105664T priority patent/DE3374749D1/de
Priority to EP83105664A priority patent/EP0096854B1/en
Publication of JPS58215841A publication Critical patent/JPS58215841A/ja
Publication of JPH0472423B2 publication Critical patent/JPH0472423B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57099704A 1982-06-10 1982-06-10 フレ−ム同期方式 Granted JPS58215841A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP57099704A JPS58215841A (ja) 1982-06-10 1982-06-10 フレ−ム同期方式
US06/501,729 US4541104A (en) 1982-06-10 1983-06-06 Framing circuit for digital system
CA000430005A CA1195007A (en) 1982-06-10 1983-06-09 Framing system
DE8383105664T DE3374749D1 (en) 1982-06-10 1983-06-09 Framing system
EP83105664A EP0096854B1 (en) 1982-06-10 1983-06-09 Framing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57099704A JPS58215841A (ja) 1982-06-10 1982-06-10 フレ−ム同期方式

Publications (2)

Publication Number Publication Date
JPS58215841A JPS58215841A (ja) 1983-12-15
JPH0472423B2 true JPH0472423B2 (enrdf_load_stackoverflow) 1992-11-18

Family

ID=14254443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57099704A Granted JPS58215841A (ja) 1982-06-10 1982-06-10 フレ−ム同期方式

Country Status (1)

Country Link
JP (1) JPS58215841A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS58215841A (ja) 1983-12-15

Similar Documents

Publication Publication Date Title
EP0096854B1 (en) Framing system
US4032885A (en) Digital correlator
US6212660B1 (en) Methods and apparatuses for identification of the position of data packets which are located in a serial received data stream
US4506372A (en) Method and apparatus for recognizing in a receiver the start of a telegram signal consisting of a bit impulse sequence
US4747105A (en) Linear feedback sequence detection with error correction
CA1212723A (en) System for transmitting digital information signals
US5228036A (en) Frame synchronization stabilizer
US4959834A (en) Word syncronization system and method
JPH0472423B2 (enrdf_load_stackoverflow)
US3678200A (en) Frame synchronization system
JPS6340509B2 (enrdf_load_stackoverflow)
RU2810267C1 (ru) Устройство синхронизации кодовых комбинаций
RU2812335C1 (ru) Способ синхронизации кодовых комбинаций
JPS585543B2 (ja) フレ−ム同期装置
US6307904B1 (en) Clock recovery circuit
JPS5819177B2 (ja) フレ−ム同期回路
JP2626900B2 (ja) ブロック同期方式
RU2231228C1 (ru) Устройство для синхронизации по циклам
KR950010919B1 (ko) 코드의 쉬프트와 가산 특성을 이용한 동기획득 장치 및 방법
SU1035820A1 (ru) Цифровое устройство слежени за задержкой
JPS648942B2 (enrdf_load_stackoverflow)
JP3163399B2 (ja) 並列形フレーム同期回路
JPS60183837A (ja) フレ−ム同期方式
SU1172052A1 (ru) Устройство дл синхронизации по циклам
SU1324091A1 (ru) Генератор псевдослучайных чисел