JPH0471209B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a waveform generation control device, and in particular, to a central processing unit (hereinafter referred to as
By doing this without the intervention of a CPU (referred to as a CPU)
This invention relates to a waveform generation control device that is realized without reducing the processing capacity of a CPU.

Background of the Technology For example, mechatronics control requires a waveform that is a complex combination of pulses with a narrow pulse width of 10 microseconds. When such high-speed and complex waveforms are generated by a microcomputer, it is extremely difficult to generate them under CPU control because the number of instructions becomes too large.

Conventional technology and problems Conventionally, devices equipped with control and arithmetic functions, such as control devices that use a microprocessor as their CPU, have been equipped with general-purpose peripheral LSIs called programmable timers (for example, Intel Corporation) to generate high-speed waveforms. i8253, 8254, Motorola MC6840
etc.) are used to control waveform generation.
This programmable timer has various modes, and for example, by using the function of an autoload timer, it is possible to generate pulses of arbitrary duty.

However, in the waveform generation control using the programmable timer described above, it is necessary to provide an external counter circuit to count the number of pulses even when controlling the waveform in a slightly complicated manner, for example, when outputting 10 pulses with a period of 4 microseconds. Therefore, there are problems in that it lacks versatility and is expensive. Also, for example, in order to slightly change the waveform cycle to produce sound or to output an irregular waveform, the data in the control register in the programmable timer needs to be reset by the CPU each time. There is also the problem that the processing capacity of

Purpose of the Invention In view of the problems in the prior art described above, an object of the present invention is to provide a versatile, low-cost, and
An object of the present invention is to provide a waveform generation control device that can generate complex waveforms at high speed without causing a decrease in processing capacity.

Configuration of the Invention In order to achieve the above object, the present invention provides a central processing unit equipped with control and calculation functions, and a waveform generator that generates a voltage waveform that changes over time. In the control device, a writable/readable memory in which waveform information consisting of pulse width values and pulse interval values of a waveform to be generated and control information for controlling how to read this waveform information are written by the central processing unit. By reading and decoding the control information stored in the device and the storage device, the read address of the storage device is determined independently of the control of the central processing unit, and the waveform generator determines the read address by the storage device control circuit. A waveform generating device is characterized in that it generates a waveform based on waveform information read out from a storage device using the present invention.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram showing a waveform generation control device according to an embodiment of the present invention. In the figure, 1 is a CPU equipped with control and calculation functions;
is a waveform generation circuit that generates a voltage that changes over time; 3 is a random access memory (RAM); 4 is a random access memory (RAM);
is the RAM control circuit. Waveform information and control information for controlling this waveform information are written in the RAM 3 in advance by the CPU 1. RAM3 of these information
Writing may be performed via the RAM control circuit 4, or may be written directly from the CPU 1 via the bus 5 indicated by the dotted line in the figure. In any case, RAM3
After the above-mentioned information is written once, the RAM 3 and the RAM control circuit 4 are not controlled by the CPU 1 except when rewriting for updating.
The RAM control circuit 4 reads control information from the RAM 3 via the bus 6, decodes the control information, and determines a read address for reading waveform information from the RAM 3. The determined read address is given to the RAM 3 via the bus 7, whereby the waveform information is read out and input to the RAM control circuit 4 and the waveform generation circuit 2. The RAM control circuit 4 determines the next read address from the received waveform information and the control information already stored, and the read continues in this manner. The waveform generation circuit 2 sends out a high-level or low-level signal, that is, a pulse train, based on the received waveform information.

FIG. 2a is a diagram showing a pulse train obtained by an embodiment of the present invention, and FIG. 2b is a diagram schematically showing information stored in the RAM 3 to obtain the pulse train of FIG. 2a. In the example shown in Figures 2a and b,
The RAM control circuit 4 counts down the value stored at one address in the RAM 3, and when it reaches 0, automatically loads the value from the next address and starts counting. As shown in Figure 2a,
The nth period and (n
+1) If we perform waveform control with an interval of (100+10×n) microseconds during the period, Figure 2b
As shown in the figure, RAM3 has 10, 50, 10, 50,
Waveform information such as 10, 50, 10, 110, . . . may be stored. In this case, the control information is
Information C for performing the above control is stored in the RAM 3, and the RAM control circuit 4 decodes the information C to perform the above control of counting down the waveform information and loading the waveform information at the next address.

In order to perform the control shown in Figure 2a using a conventional programmable timer, it is necessary to add external hardware logic for gate signals and to access registers frequently, which increases the CPU load and increases the CPU load. If the CPU is used for other purposes, the generation of fast waveforms such as 10 microsecond pulse widths may become impossible.

FIG. 3 is a diagram showing the contents of RAM 3 according to another embodiment of the present invention. In FIG. 3, more complex control information is stored in RAM3. That is, in the example of FIG. 3, the RAM control circuit 4
By decoding the control information LOOP 4 AND JUMP A, the waveform information H=10 and L=50
is read 4 times and outputs 10 microsecond width pulses 4 times at 50 microsecond intervals, then jumps to address A and reads H=0 and L=60 at 60 microsecond intervals, then LOOP 4 AND JUMP B
By decoding the control information H=10
Waveform generation control is performed by reading out and L=50 four times, outputting 10 microsecond pulses four times at 50 microsecond intervals, and then jumping to address B with an interval of 70 microseconds. .

In any of the embodiments, it is noted that once the single waveform information and control information are stored in the RAM 3, the CPU does not participate in waveform generation control. Therefore, even if the CPU is used for other purposes,
A narrow pulse of 10 microseconds can be obtained. Further, even when performing complex waveform control, there is no need to add a new external counter circuit or hardware logic.

The present invention is not limited to the embodiments described above, and by storing desired control information and desired waveform information in the RAM 3, various waveform controls are possible.

Effects of the Invention As explained above, the present invention provides a waveform generation control device that is versatile, inexpensive, and capable of generating complex waveforms at high speed without reducing the processing power of the CPU. .

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a waveform generation control device according to an embodiment of the present invention, FIG. 2a is a diagram showing a pulse train obtained by an embodiment of the present invention, and FIG.
FIG. 2B is a diagram schematically showing information stored in the RAM to obtain the pulse train of FIG. 2A, and FIG. 3 is a diagram showing the contents of the RAM according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Waveform generation circuit, 3...Storage device, 4...Storage device control circuit.

Claims (1)

[Claims] 1 Central processing unit equipped with control and calculation functions,
and a control device equipped with a waveform generator that generates a voltage waveform that changes over time, in which the central processing unit reads out waveform information consisting of pulse width values and pulse interval values of the waveform to be generated, and the waveform information. A writable/readable storage device in which control information for controlling the computer is written, and the control information stored in the storage device is read and decoded to control the storage device independently of the control of the central processing unit. A read address of the device is determined, and the waveform generating device generates a waveform based on waveform information read from the storage device using the read address by the storage device control circuit. Waveform generator.