JPS6120417A - Programmable pulse generator - Google Patents

Abstract

PURPOSE:To execute programming by an MPU, and also to obtain a pulse train at a higher speed than its processing speed by providing a memory which can be written by the MPU, and a counter which is stepped by an individual clock and also can be set by the MPU. CONSTITUTION:In a write period, an address is given directly to a memory M from an address output terminal AOUT of an MPU, data is give to the memory M through a buffer B1 from a data output terminal DOUT, and storage is executed to the memory M by the timing of a write signal WR and a chip selecting signal CS. On the other hand, when entering a generation period of a pulse, a counter CNT is reset by the MPU, stepped in accordance with a clock signal, and continuous address are given to the memory M. Also, a clock signal inverted by an invertor I is applied to a D - FF, therefore, after an output of the memory M has been resolved completey, data is inputted, and outputted as a pulse to an outputted as a pulse to an output terminal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable pulse generator that can be programmed by a microprocessor and is capable of obtaining a pulse train with timing faster than the processing speed of the microprocessor.

(Prior Art) Conventionally, in order to generate a pulse train at a desired timing, a method has been used in which data stored in advance in a memory is sequentially read out using a microprocessor or the like.

In this method, data can be selected at the necessary timing according to various situations using the microprocessor, and it is extremely versatile. However, due to the structure, the memory address is assigned by the microprocessor. , because the data had to be read out, pulses could not be generated at a timing faster than the operating speed of the microprocessor.

On the other hand, a pulse generator constructed using hard logic does not have the above-mentioned drawbacks, but it has the disadvantage that it is difficult to change the timing of the pulses it generates, which limits its applications.

(Object of the Invention) The present invention has been proposed in view of the above points, and its purpose is to provide a timing program that can be programmed by a microprocessor and that is faster than the processing speed of the microprocessor. An object of the present invention is to provide a programmable pulse generator capable of generating a pulse train.

(Structure of the invention) DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments.

The figure is a circuit configuration diagram showing an embodiment of the present invention. To explain the configuration in the figure, the circuit mainly includes a microprocessor MPU, a memory M having a 1-bit data output, and a counter CWT for giving an address to the memory M.
, a flip-flop D for holding the output of the memory M
- It is composed of FF. Further, a write number WR and a chip select signal C3 are applied to the memory M from the microprocessor MPU, and a reset signal R is applied to the counter CNT. Note that B is a buffer for writing data into memory M, and B2 and B8 are buffers for alternately transmitting the address given from microprocessor MPU to memory M and the address given from counter CNT to memory M. It is a buffer.

On the other hand, the counter CWT is incremented by a clock signal supplied from a clock oscillator CLK, and the clock signal is also supplied to the clock input terminal CK of the flip-flop D-FF via an inverter (2).

Therefore, the operation is divided into a data write period and a pulse generation period. That is, during the data write period, the address output terminal A of the microprocessor MPU. An address is directly given to memory M by U, data is given to the data input/output terminal of memory M from data output terminal DoU□ via buffer B, and data is sent to memory M at the timing of the write signal and chip select signal. Memory takes place. Note that this data writing is performed before pulses with high-speed timing are required.
This is done during a rest period in which no pulse generation is required. Further, if there is no change in the already stored data, there is no need to write the data.

On the other hand, when the pulse generation period begins, the microprocessor M
The counter CWT is reset by the PU and increments in accordance with the clock signals given from the tarlock oscillators CI and K, giving continuous addresses to the memory M. t: Since the flip-flop D-FF is given a clock signal inverted from that of the counter CNT by the inverter l,
After the output of the memory M is completely determined, the data is taken in and output as a pulse to the output terminal OUT.

(Effects of the Invention) As described above, the present invention includes a memory into which data can be written by a microprocessor, and a counter that is incremented by an individual clock and can be reset by the microprocessor. After writing data to the memory, the address of the memory is sequentially given by the counter, and a pulse train is output from the memory at the timing of the clock, so that programming is possible with a microprocessor, and the processing by the microprocessor is easy. This has the effect of being able to obtain a pulse train with a timing faster than the speed.

[Brief explanation of drawings]

The figure is a circuit configuration diagram showing an embodiment of the present invention. MPU...Microprocessor, M...Memory,
CWT...Counter, CLK...Clock 'A swing N'
, D-FF... Flip-flop, ■ - Inverter, B. B2. B3゛°Buffer and 1 other person

Claims (1)

[Claims] comprising a memory into which data can be written by a microprocessor, and a counter that is incremented by an individual clock and can be reset by the microprocessor;
A programmable pulse generator characterized in that after writing data to the memory, addresses of the memory are sequentially given by the counter, and a pulse train is output from the memory at the timing of the clock.