JPS60205896A - Timing control circuit - Google Patents

Abstract

PURPOSE:To shorten the repeating cycle of a timing signal by inhibiting selectively the holding function of a register which delivers the timing signal synchronized with a clock. CONSTITUTION:Registers 11 and 12 contain a holding terminal H and a data terminal D and have the holding functions of an FF, etc. to which clock pulses are supplied and are controlled via NAND gates 15-17 and 25-27 respectively. The outputs of both registers 11 and 12 are supplied to an AND gate via variable delay circuit 12 and 22 and selection circuits 23 and 24 respectively. Thus a desired timing signal synchronized with a clock is delivered. While the holding functions of the registers 11 and 12 are inhibited by the external control via a positive/ negative polarity driver. Then the limitation is released for a range of output waveforms. Thus it is possible to produce a timing signal of a repeating cycle approximate to a clock cycle less than 4 times as much as the clock.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a timing adjustment circuit, particularly a dynamic RA
The present invention relates to a timing adjustment circuit for supplying a timing signal to a memory element such as M or static RAM.

(Prior Art) In general, a memory circuit operates synchronously using a timing signal generated based on an internal clock when reading or writing the memory circuit. Pulses used as timing signals are synchronized with a clock, but generally the rise time, pulse width, fall time, pulse interval, etc. need to be finely adjusted depending on the purpose of use.

Conventionally, the circuit shown in FIG. 1 has been widely used as a timing adjustment circuit for generating such timing pulses.

As will be detailed later, this circuit inputs two control input signals IN1' and IN2' to a register with a hold function.
' and 21', and a delay circuit consisting of delay circuits *x2' and '22' and selection circuits 13' and 23', and then by combining them, the rising time, pulse width, It is conveniently used as a timing adjustment circuit because it can generate pulses whose pulse intervals are adjusted according to the purpose at the 9th falling point.

However, as will be explained later, according to this circuit,
If you try to make the pulse width close to the clock period (hereinafter referred to as T) and make the interval between successive pulses as small as possible, it has the disadvantage that the repetition period cannot be made as small as 4T. The use of this circuit is limited, and it is not suitable when the same circuit is used for both dynamic RAM and static RAM. (Objective of the Invention) The purpose of the present invention is to It is an object of the present invention to provide a timing adjustment circuit which retains the characteristics as is and eliminates the above-mentioned drawbacks.

(Structure of the Invention) The circuit of the present invention includes two registers having a hold function, a first operation mode that operates using the hold function of the register, and a circuit that operates with the hold function of the two registers prohibited. a logic circuit whose second operation mode can be selected by an external control signal; and two delays which are connected to the output of each of the registers and whose delay time can be adjusted by an external selection signal. and an output circuit for logically synthesizing the outputs of the delay circuits.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the first Lujistar 11. First delay circuit group 12, first
Selection circuit 13. ANDGATE 14. Nantes Gate 15,
16.17+second register 21. , second delay circuit group 22
．． Second selection circuit 23. ANDGATE 24. Nantes Gate 25, 26.27. It has a positive/negative polarity driver 30 and an AND gate 4o.

The second register 21 and the second register 21 are seven lip-flop circuits having a D input terminal and an H input terminal.
It performs operations in synchronization with a supplied internal clock (not shown). That is, the signal supplied to the H input cursor is 0.
In the case of #, it is set to u1n/competition 0# according to the data of the D input terminal at the clock time, 1"/0". Furthermore, when the signal supplied to the H input terminal is 11", the logic value currently set in the register is 1".
"/uO" is held as is until the next clock point.

Q is an output for outputting this set logical value to the outside as it is, and Q is an output for inverting this set logical value and outputting it to the outside.

Delay circuit group 12. The selection circuit 13 forms a variable delay circuit, and the selection signal 1300
Accordingly, the delay element output of an appropriate step in the delay circuit group 12 is selected by the circuit 13 to control the amount of delay.

Similarly, the delay circuit group 22 and the selection circuit 23 also receive the selection signal 2.
The output of the circuit 13 and the output of the circuit 23 (with polarity inversion) are combined by an AND gate 40 to form the output circuit of this embodiment. As a result, as will be described later, the delay circuit composed of the first delay circuit group 12 and the first selection circuit 13 is activated at the rising edge of the output pulse (from 10" to '@1").
The delay circuit composed of the second delay circuit group 22 and the second selection circuit 23 is used to control the falling point of the output pulse (from 11" to @θ It is used to control the point at which the change occurs.

Now, in the circuit of this embodiment, the mode control signal input terminal 30
0, and the mode control signal MO"l added here
”/@0# It operates in two-pass mode.

In other words, when the mode control signal M1k is set to "1", 14.24. ``1'' is constantly supplied to Nant Gate 15.25, and Nand Goo) 16.
As a result, the circuit of this embodiment is equivalent to the circuit shown in Fig. 3. This is the same as the conventional circuit shown in Fig. M1. This will be referred to as the first mode operation.

On the other hand, when the mode control signal M is set to 'O', the AND gates 14, 24.
10" is constantly supplied to the
．． As a result of the constant supply of 11'' to 26, the circuit of this embodiment becomes equivalent to the circuit shown in FIG.

This will hereinafter be referred to as the second mode operation.

The first mode operation and the second mode operation will be explained below.

[First mode operation] As mentioned above, '1' is input to the mode control signal input terminal 300.
is supplied, the circuit operates in the first mode and becomes completely equivalent to the circuit shown in FIG. Therefore, the operation will be explained below with reference to FIG. FIG. 5 is a timing chart showing the operation in the first mode.

Now, as the initial state, register 11 and register 2
It is assumed that both Q outputs of the register 11 and C are 10'' in the time chart of FIG. 5. E, which is the Q output of the register 21, is 11''.

In this state, the first control input terminal 150 (IN
Assume that a control signal having a pulse width of approximately the clock period T is supplied to I). Currently, MQ'' is clearly being supplied to the H terminal of register 11, so at the next clock time TO, register 11 is set to ul'' and from that point on, A becomes 1''. ] The H terminal of the register 11 becomes 1", so even if the input INI becomes aO", the register 11 holds the value of @1", and therefore A maintains the value of 1".

In this state, on the register 21 side, the AND gate 25' allows the input signal from the second control input terminal 250 (IN2) to pass, and since the H terminal input is "0", the Ts degree is applied to IN2 at the time t3. If a control signal with a pulse width of
1 is set to @1#, so C goes from @0'' to @1
”, and E changes from “@1” to IO”. Therefore, both the H input terminal and D input terminal of the register 11 are 10".
Therefore, at the next clock time TC3, the register 11 is reset to @0'' and A returns to uO''.

When A returns to 0, both the H input terminal and the input terminal on the register 21 side become lO'', so at the next clock time TC, the register 21 is reset to tIO'', and therefore T
At e3, C returns from -1" to uO" and E returns from @0" to ul", thereby returning to the initial state in which both register 11 and register 21 have been reset. Therefore, by applying the INI control pulse again after 1°C4, for example at t4, the above operation can be repeated from the beginning.

Now, the Q output A of the register 11 passes through a delay circuit composed of a delay circuit group 12 and a selection circuit 13, so that it is delayed by a delay amount D1 and becomes an output B that rises from time t2. As described above, this delay amount D1 can be adjusted stepwise by the selection signal 1300.

Further, the Q output C of the register 21 is also delayed in the same manner as above, and produces an output D' which falls from time t4 after a delay (the output on the second selection circuit 23 side is inverted). By combining these B and D' with the AND gate 40, the output F can be obtained.

The output F obtained in this way has a rising leading edge of 1° as a signal 1.
Fine adjustment is possible with 300, and the trailing edge t4
can be finely adjusted using the signal 2300. Moreover, the pulse width from 1 to t4 can be changed in steps of T by adjusting the relative relationship between the signal IN1 and the signal IN2. Able to freely generate wide pulses - The operation of 6 or more first motes: 5 provides timing pulses as described above, which allows the timing adjustment circuit to have a wide range of applications. It can be used for feces.

However, due to the operation in the first mode described above,
If you try to repeat a pulse with a width of about IT at as short an interval as possible, the operation shown in Figure 6 will occur, and as is clear from the figure, the pulse repetition interval will be made smaller than 4T. I can't.

As mentioned above, conventional circuits have these drawbacks.

On the other hand, the circuit of this embodiment has a second mode operation,
This problem has been resolved.

This second mode operation will be explained below.

[Second mode operation] As mentioned above, when the mode control signal input terminal 300 is connected to the
is supplied, the circuit operates in the second mode and becomes completely equivalent to the circuit shown in FIG. Therefore, the operation will be explained below according to FIG. 4. FIG. 7 is a timing chart showing the second mode operation.

Now, as shown in FIG. 4, in the second mode operation, 10# is constantly supplied to the H input terminal of both register 11 and register 21, so the hold function of these registers is prohibited and control is disabled. Input terminal 150 (
The logical values applied to INI) and 250 (IN2) will remain set at the clock instant.

Now, when both register 11 and register 21 are initially in the reset state (that is, both A and C are 10"
), at the time point 11 in FIG. 7, the clock period T
A control signal having a pulse width of about
〇 Then, the next clock time TC!
At this point, both registers 11 and 12 are set to 1#, and from that point on, A and C become 1#.

Next, at the next clock time TC, both INI and IN2 have already returned to @O'', so both register 11 and register 21 are at @0'' at this point.
will be reset to

Therefore, time 1 . before the next clock time TCs arrives. , the same control signals as above are again applied to -INI and I
By adding it to N2, it is possible to make it rise again to 61" from the time of A and Ct-TC. Now, as mentioned above, the Q output A of register 11 is output by the delay circuit after the delay amount D1. The Q output C of the register 2-1 produces an output that falls from t4 after a delay of 1.1.

By combining these B and Dl with the AND gate 40, 9F is obtained. As is clear from FIG.
Fine adjustment is possible with signal 2300 and trailing edge t4 (falling edge) can be finely adjusted with signal 2300. By appropriately selecting the pulse width from t3 to t4 as the delay amount D1, it is easy to freely select from a very narrow pulse width to a pulse width approximately equal to IT.

Moreover, as is clear from Fig. 7, INI and IN2
The pulse output Ft-2 adjusted as described above by applying the same control signal of about 11 width every 2T to
This makes it possible to cover a range that could not be obtained in the first mode of operation described above.

The above description shows one embodiment of the present invention, and the present invention is not limited thereto. For example, each gate 14 to 17, each gate 24 to 27, and driver 30 shown in FIG.
The logic circuit consisting of can also be replaced with another logic circuit that operates equivalently.

(Effects of the Invention) As described above, according to the present invention, two registers having a hold function can be used in a first mode operation that utilizes this hold function and a second mode operation that uses this hold function while inhibiting it. By operating in two modes, it is possible to eliminate the limitation in the range of waveforms that can be generated, which is a disadvantage of conventional circuits.

In other words, it is possible to output a long pulse signal with a pulse width several times the clock period.1. A pulse signal f having a pulse width close to the clock cycle and an adjusted waveform can be outputted repeatedly at every twice the clock cycle.

Furthermore, by converting the circuit tL81 of the present invention into a type of LSI, it can be used in a variety of applications, and since the delay circuit group can be configured with gates in the same LSI, the adjustment unit can be made smaller. A timing adjustment circuit having an adjustment circuit with little variation can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIGS. 3 and 4 are circuit diagrams for explaining the operation of the embodiment, and FIG. , Figures 6 and 7
The figure is a time chart for explaining the operation of the embodiment. In the figure, 11...second register, 12...first register
Delay circuit group, 13... first selection circuit, 14... AND gate, 15t16+17... Nants gate, 21
...Second register, 22...Second delay circuit group, 23
... second selection circuit, 24 ... and gate, 25,
26.27...Nant gate, 30...Positive/negative polarity driver, 40...And gate. Mi ■OQ Mi ■O■ ■ ■ Figure 7

Claims (1)

[Claims] Two registers having a hold function, a first operation mode that operates by utilizing the hold function of the registers, and a second operation mode that operates by disabling the hold function of the two registers. two delay circuits connected to the output of each of the registers and whose delay time can be adjusted by an external selection signal; A timing adjustment circuit comprising: an output circuit for logically synthesizing outputs of the circuits.