JPS61126691A - Refreshing circuit of memory - Google Patents

Abstract

PURPOSE:To secure the number of times of the minimum refreshing cycle necessary to a dynamic RAM without stopping a CPV for a long time by counting the number of the machine cycle in which one refreshing is necessary and stopping a final machine period CPV at the time of necessities. CONSTITUTION:A counter 1 reset, when a dynamic RAM (DRAM) selecting signal is not generated from an address decoder 1, counts the number of the machine cycle of CPV where one refreshing is necessary, arrives at the number of the machine cycle, and then, a CPV stop requesting signal is generated. In response to the signal, a CPV stop confirming signal is supplied through an or gate 13, a refreshing pulse is generated from a refreshing pulse generating circuit 2, at the final machine cycle a CPU is stopped and refreshed. The counter 11 refreshed by a machine cycle before the final value reaches is reset. Thus, without stopping the CPU for a long time, the minimum refreshing cycle necessary to a DRAM can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic random access memory (D
This invention relates to a memory refresh circuit that guarantees the standard number of refresh cycles per unit time under any conditions and achieves memory refresh without reducing the efficiency of a processing unit (CPU).

[Conventional technology]

Conventionally, dynamic random access memory (DRAM)
) is, for example, a capacitor-type mesori element provided at the intersection of the matrix, and refreshing is performed by selecting and charging an excitation line in the row or column direction. In order to use this DRAM under the control of the OPU and retain its data, it is necessary to ensure the number of refresh cycles within a unit time specified by the standard, and the precise hardware that performs this refresh cycle is required. Provided. Conventionally, various methods have been used to determine when to obtain this refresh cycle.

An example of this is shown below: As the simplest method, as shown in FIG.
Outputs the M select signal and inverts it in parallel.
The refresh pulse generating circuit 2 is operated to output refresh pulses during a period when the RAM is not accessed.

The disadvantages of this method are the software configuration, high-speed DMA'
, Ilo, etc., the number of refresh cycles required by the standard may not be guaranteed.

In order to compensate for the shortcomings of FIG. 3, the system shown in FIG. 4 includes a counter 3 which is branched before the refresh pulse generation circuit 2 and monitors whether the number of refresh cycles is within the standard. A forced refresh request circuit 4 is provided which operates according to the result, and the operation period of the refresh pulse generation circuit 2 is controlled by this output.

That is, when the number of refreshing operations within the standard cannot be obtained from the result of the refresh cycle counter 3, the OPU is forcibly stopped for a period long enough to perform refreshing the number of times that is insufficient, and refresh is performed. This makes it possible to secure the required number of refreshes.

[Problem that the invention seeks to solve]

Although the method shown in Figure 4 secures the number of times the DRAM is refreshed, since the OPU is forcibly stopped for a certain period of time, the efficiency of the OPU temporarily decreases for a long period of time, and the use of other controlled objects is interrupted. This results in considerable limitations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM refresh circuit that guarantees the minimum number of refresh cycles necessary for refreshing a dynamic RAM and eliminates the need for a long pause in OPU for refresh. It's about doing.

[Rounding method to solve problems]

In order to achieve the above object, the memory resetting circuit of the present invention includes means for selecting a machine cycle to refresh a memory whose refresh is controlled by a processing device, and a means for selecting the number of machine cycles that require at least one refresh. Means to count and the number of machine cycles at the end of the period! The machine is characterized by comprising means for completely detecting the absence of a refresh cycle before a thin cycle and stopping the processing device at the final machine cycle, and means for generating seven refresher pulses during the stop period of the processing device. It is.

[For production]

The above configuration introduces a large minimum number of refresh cycles during which the dynamic RAM retains its contents, and before the last machine cycle of this period, the normal OPU
If there is a delay in not accessing the DRAM during operation, the OPU is reset, and if there is no refresh, the OPU is stopped and refreshed only during the final machine cycle. In this way, the minimum number of refresh cycles is guaranteed by cooperating with normal non-access refresh of DRAM. Sara 4
Since it takes only one machine cycle to stop the CPU, there is no adverse effect on other objects controlled by the CPU.

(Embodiment) Fig. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, and Fig. 2
-■ show operation waveform diagrams of main parts of the embodiment.

In the present invention, in order to prevent the temporary decrease in CPU efficiency, which is the drawback of FIG. 4, only the number of machine tickles that require refreshing is detected and performed.

As a general RAM refresh standard, 1
We will discuss the case of 28 cycles or more/2 ms. Also, one machine cycle of the CPU is 5o.

Assume case 1.

The number of machine cycles required for at least one refresh cycle under these conditions is calculated as follows.

(200α/128)/(L5=3L25 (machine cycles)) (1) Therefore, at least 1 per 3t25 machine cycles
With 1 refresh cycles, the memory contents are retained and the 128 @/2 ms standard can be met.

In FIG. 1, a counter 11 is provided to count machine cycles that require at least one refresh cycle, 3t25 machine cycles in this example, and when there is no DRAM select/select signal output from the address decoder 1, the inverted signal is reset. The machine clock when there is a DRAM select signal is input to the clock terminal via the AND circuit 12, and the counter 11 inputs the DRAM select signal to the clock terminal.
It is reset when there is no RAM select signal, and counts when there is the select signal. Specifically, when there is no refresh cycle for 31 consecutive machine cycles, only one next cycle is set as a refresh cycle, and the CPU is stopped for this one machine cycle period. The 31st monitoring was carried out using the counter 11,
Counting up of the counter 11 is performed by pulses synchronized with non-refresh cycles. If there is a refresh by the 31st time, the counter 11 is reset,
If there is no refresh, an OPU stop request is output as 0PUK in the final machine cycle after counting 31 times. Then, when the CPU returns a CPU stop confirmation signal,
This is input to the refresh pulse generation circuit 2 via the OR circuit 13, and the refresh pulse is sent to the DRAM').
9 refresh is performed.

FIGS. 2 - 2 show the waveforms of the machine clock (2), the CPU stop request (2) of the counter output, the CPU stop/stop confirmation signal and the refresh signal related to this forced refresh cycle. In other words, there is no refresh from the machine clock number 0 to number 30 of ■, and the OPU stop request of number ■ is OPENed from the counter 11 at the machine clock number number 31.
U, and after one clock delay, the CPU stop confirmation signal (■) is sent to the refresh pulse generation circuit 2 via the OR circuit 13.
, and generates the refresh pulse of
f) Refreshing is performed by adding, for example, 9 in the column direction.

Since the OPU resumes operation immediately after this forced refresh cycle is executed, the OPU can be stopped for a short time. Note that the generation of refresh cycles other than this forced refresh cycle is the same as in FIG. Start.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to count the number of machine cycles that require at least one refresh for a dynamic process λM, and to determine that there is no refresh address before the last machine cycle in the period of the number of machine cycles. is detected and the OPU is stopped only for the last machine cycle. This is j9, DR
The minimum number of refresh cycles required for AM refresh is guaranteed, and O
Since the PU does not have to pause for a long time, an improvement in CPU efficiency can be expected.

[Brief explanation of drawings]

(Fig. 1 is an explanatory diagram of the configuration of the embodiment of the present invention, Fig. 2 is an operational waveform diagram of the main part of the embodiment, and Figs. 3 and 4 are explanatory diagrams of the configuration of the conventional example, respectively). 1 is an address Decoder, 2 is a refresh pulse generation circuit, 11 is a counter, 12 is AN
D circuit, 13 shows an OR circuit.

Claims (1)

[Claims] means for selecting a machine cycle to refresh a memory that is refresh-controlled by a processing unit; means for counting the number of machine cycles that require at least one refresh; and refreshing before the last machine cycle of the period of the number of machine cycles. 1. A memory refresh circuit comprising: means for detecting the absence of a cycle and stopping a processing device only for the last machine cycle; and means for generating a refresh pulse during a period in which the processing device is stopped.