KR960001110B1 - Dynamic ram(dram)refresh system - Google Patents

Abstract

The device comprises a memory controlling unit which outputs control signals, a memory unit which refreshes memory cells belong to the fixed addresses, and a refresh controlling unit which outputs refresh require signals to the memory controlling unit, stops operating until refresh acknowledge signals is supplied by the memory controlling unit, and outputs refresh address signals to the memory unit by inputting refresh clocks from the memory controlling unit.

Description

Dynamic RAM Refresh System

1 is a block diagram of a refresh system according to the present invention.

2 is an internal circuit diagram of a refresh controller.

3 is a timing diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: Memory Controller 2: Refresh Controller

3: memory unit 4: refresh counter

5: refresh address counter 6: inverter

7: D flip-flop 8: MUX flip-flop

The present invention relates to a DRAM refresh system capable of controlling DRAM by generating a required signal through a dedicated refresh control circuit on a system using dynamic RAM.

In general, it is inconvenient to design a DRAM refresh using a DMA channel and a timer channel, and to design a priority setting as a DRAM refresh.

The present invention devised to solve the above problems, by using a dedicated refresh controller that can implement a DRAM refresh without using a direct memory access (DMA) and a timer, reducing the number of gates in ASIC design, prioritizing DRAM refresh The purpose is to provide a dynamic RAM (DRAM) refresh system that enables simple design because it does not need to be designed to rank, but only on hardware, without the need for software programs.

In order to achieve the above object, the present invention provides a memory controller for outputting predetermined control signals, and a memory for refreshing memory cells belonging to a specified address when a refresh address signal is applied during a read / write operation under the control of the memory controller. In a dynamic ram refresh system having a part; When the video clock is externally synchronized to perform a count, and if the count value is full, a predetermined number is output, the refresh request signal is output to the memory controller by internal control, and the refresh recognition signal is applied from the memory controller. The apparatus may further include a refresh controller unit which stops driving until it receives a refresh clock signal from the memory controller unit, counts a predetermined number, and outputs a refresh address signal to the memory unit.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a block diagram of a refresh system according to the present invention, and FIG. 2 is an internal circuit diagram of a refresh controller. In the drawings, 1 is a memory controller, 2 is a refresh controller, 3 is a memory unit, 4 is a refresh counter, and 5 is a block diagram of a refresh controller. Denotes a refresh address counter, 6 denotes an inverter, 7 denotes a D flip-flop, and 8 denotes a MUX flip-flop.

As shown in FIG. 1, the refresh system according to the present invention comprises a memory controller 1, a refresh controller 3, and a memory unit 3, and the function of each component is as follows.

The memory controller 1 is a main controller for controlling the memory unit 1 and controls CPU write / read, refresh to the monitor and DRAM refresh according to priority. Therefore, the corresponding address and the control signal are input to the memory unit 3 by the final control of the memory controller 1.

The refresh controller 2, which starts to operate when power is applied, receives a video clock from an external source and keeps counting in synchronization. Since the internal counter is 9 bits, when the count value becomes 1023, the internal counter outputs a refresh request (ref_req) signal to the memory controller 1 by internal control, and the internal counter recognizes the refresh from the memory controller 1. The driving stops until a (ref_ack) signal is applied. Stop. After receiving the refresh clock ref_clk signal from the memory controller 1, a predetermined number is counted, and an address is output to the memory unit 3.

The memory unit 3 performs a read / write operation under the control of the memory controller 1 and refreshes the memory cell when an address signal is applied from the refresh controller 2.

As shown in FIG. 2, the refresh controller 2 counts a video clock signal input from the outside, and outputs a high level signal to its output terminal CO when the predetermined number is counted. An inverter 6 for inverting the output of the refresh counter 4 in response to a clock signal, a D-flop 7 for receiving an output of the inverter 6 and outputting an inverted signal synchronized with the video clock; A MUX flip-flop 8 which uses the refresh recognition signal ref_ack as a selection signal from the controller 1 and selects one of the ground signal and its own output signal in response to this signal and outputs the refresh request signal ref_req; A refresher that receives a refresh clock signal ref_clk from the memory controller 1 and counts it, and then counts a predetermined number to output a refresh address signal to the memory unit 3. It consists of a dress counter 5.

Looking at the operation and the effect of the present invention having the above configuration, the counter bit of the refresh counter (4) and the refresh address counter (5) is a synchronous counter, and when the count value reaches a maximum value of 1023 refresh The counter 4 outputs a high level signal through its output terminal C0, and the output signal is applied by the inverter 6 to the input terminal D of the inverted door D flip-flop 7.

Then, the flip-flop 7 outputs an input signal in response to the video clock signal as an inverted signal. The inverted output is applied to the preset terminal of the MUX flip-flop 8 so that the MUX flip-flop 8 is initialized. Its output terminal Q generates a high level signal. This high level signal becomes the refresh request signal ref_req, and the refresh request signal ref_req is provided to the memory controller 1.

On the other hand, since the inverted output Qn of the MUX flip-flop 8 is applied to the chip enable terminal CI of the refresh counter 4, the refresh counter 4 counts even when a video clock signal is inputted to its clock terminal. It does not work. This has the advantage that the counter value is maintained until the memory controller 1 emits the refresh request signal ref_req so that the refresh of the DRAM does not necessarily have to be designed to be the highest priority.

The memory controller 1 receiving the refresh request signal ref_req from the MUX flip-flop 8 sequentially generates the refresh recognition signal ref_ack and the refresh clock signal ref_clk in a predetermined order.

The generated refresh recognition signal ref_ack is input to the selection terminal of the MUX flip-flop 8 to serve as a selection signal for selecting one of a ground signal and its output signal input to the MUX flip-flop 8, The refresh clock signal ref_clk is applied to the clock terminal of the refresh address count 5.

By the selection signal, the MUX flip-flop 8 selects the signal DB from its output terminal Q, while the refresh address counter 5 counts the number of 1023 and then generates the refresh address signal.

Therefore, the memory unit 3 performs a read / write operation under the control of the memory controller 1, and when the address signal is applied from the refresh controller 2, the memory unit 3 refreshes the memory cells belonging to the designated address.

3 is a timing diagram of each signal in the present invention.

Since the refresh method supports a method of refreshing only RAS (ROW ADDRESS STROBE SIGNAL), the refresh counter 2 starts counting again from zero, and the refresh counter 4 and the refresh address counter 5 It is supposed to perform count repetition.

Therefore, the present invention is a dedicated refresh controller that can implement DRAM refresh without using DMA (direct memory access) and timer, and can reduce the cost by reducing the number of gates in ASIC design, and the memory controller recognizes refresh. Since the count value is maintained until the signal is applied, it is not necessary to design the DRAM refresh as the highest priority, and the simple design is possible because it is performed only on hardware without the need for a software program.

Claims (5)

A memory controller 1 for outputting predetermined control signals, and a memory unit 3 for reading / writing operations under the control of the memory controller 1 and refreshing memory cells belonging to a specified address when a refresh address signal is applied. In a dynamic RAM (DRAM) refresh system having; When the video clock is externally synchronized to perform a count, and when the count value is full, the memory controller 1 outputs a refresh request signal ref_req to the memory controller 1 by internal control. The driving is stopped until the refresh recognition signal ref_ack is applied from (1). After receiving the refresh clock signal ref_clk from the memory controller 1, the predetermined number is counted and the memory unit 3 And a refresh controller section (2) for outputting a refresh address signal. The method of claim 1; The refresh controller 2 receives a refresh counter 4 for counting an externally input video clock signal, and is synchronized with the video clock signal, and receives the output of the refresh counter 4 and inverts the output. A flip-flop unit 7 outputting a signal to the video signal and a refresh-reception signal ref_ack received from the memory controller 1 as a selection signal and receiving a refresh signal as a ground signal or its own output signal. The MUX flip-flop unit 8 which selects one signal among the signals ref_req and outputs it to the memory controller 1, and receives a refresh clock signal ref_clk from the memory controller 1 and counts a predetermined number. And a refresh address counter section 5 for outputting a refresh address signal to the memory section 3 afterwards. System. The compound of claim 2; And the MUX flip-flop (8) receives the inverted output of the flip-flop (7) as a preset signal and is initialized by the signal. The compound of claim 2; Dynamic RAM refresh system, characterized in that the inverted output signal of the MUX flip-flop (8) acts as a chip enable signal of the refresh counter (4). The compound of claim 2; And a inverter (6) electrically connected between the output terminal of the refresh counter (4) and the input terminal of the flip-flop (7).