JPH02216697A - Dram control circuit - Google Patents

Abstract

PURPOSE:To obtain signals for control of a DRAM with a simple constitution by outputting three storage circuit outputs at different points of time in accordance with timings of clock signals. CONSTITUTION:A first storage circuit 4 which takes in an input signal by a first clock signal, a second storage circuit 5 which takes in the output signal of the first storage circuit by a second clock signal whose phase is opposite to that of the first clock signal, and a third storage circuit 6 which takes in the output signal of the second storage circuit by the second clock signal are provided. A column address signal CAS is generated a prescribed time after the generation of a row address signal RAS, and signals of the same timing as a conventional DRAM controller are sent out. Thus, signals for control of the DRAM are obtained with the simple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a RAS for controlling the operation of a DRAM.
The present invention relates to a DRAM control circuit that generates (row address signal) and CAS (column address signal) signals.

[Prior Art] As is well known, DRAM needs to be refreshed frequently, and therefore CAS and RAS need to be generated at predetermined timing. For this reason, conventionally, DRAM controllers have been provided and used in various places.

[Problems to be Solved by the Invention] However, since conventional DRAM controllers have a large shape, they have poor area efficiency, and the development of a smaller one has been awaited.

[Means for Solving the Problems] In order to solve such problems, the present invention includes a first storage circuit that receives an input signal using a first clock signal, and a first storage circuit that has a phase opposite to that of the first clock signal. The second memory circuit captures the output signal of the first memory circuit in response to the second clock signal, and the third memory circuit captures the output signal of the second memory circuit in response to the second clock signal. .

[Effect] CAS occurs a predetermined time after RAS occurs, and conventional D
A signal with the same timing as the RAM controller is sent out.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 to 3 are gate circuits that perform an OR operation on a low active input signal, and 4 to 5 are D-type flip-flops.

7 to 11 are various signals, 7 is a memory read signal, 8 is a memory write signal, 9 is a reset signal, 10 is a clock signal, and 11 is a clock signal having a phase opposite to that of the clock signal 10.

The operation of the apparatus configured as described above will be explained with reference to the time chart shown in FIG. First, memory read signal 7
Alternatively, when the memory write signal 8 is supplied, it is supplied to the gate circuit 3 and output, so that RAS is sent out as shown in FIG. 2(c).

Since the memory read signal 7 or the memory write signal 8 is also supplied to the gate circuit 1, the memory circuit 4 operates as shown in FIG.
The signal at the input terminal is taken in at the falling edge of the clock signal shown in a), and the output signal at the output terminal Q of the memory circuit 4 is changed from "0" to "1" as shown in FIG. 2(d). Among the falling points of the clock signal shown in FIG. 2(b), the output signal of the output terminal Q of the memory circuit 5 changes to "0" as shown in FIG. 2(e) at a timing immediately after the timing mentioned above.
” to “1”. Then, the output signal of the memory circuit 6 is output as shown in FIG. 2(f) at a timing immediately after the output signal (e) of the memory circuit 5 is inverted during the fall of the clock signal shown in FIG. 2(b). CAS is generated by changing from "1" to "0".

3 is a circuit diagram in which the circuit of FIG. 1 is applied to control a DRAM, 20 is the DRAM control circuit of FIG. 1, 21 is a C
PU, 22 and 23 are drivers, 24 is a DRAM, and 25 is an inverter.When the row signal and column signal are switched by the signal AS, first the ROW address is written to the DRAM at the rising edge of RAS, and then the ROW address is written to the DRAM by AS. Switch to column address and press C
The column address is written to the DRAM at the falling edge of AS. With this configuration, it can be realized with a small number of gate elements, a mini-flat or PLCC can be used, and miniaturization is possible.

[Effects of the Invention] As explained above, the present invention outputs the three memory circuit outputs at different times depending on the timing of the clock signal, so that it is possible to obtain signals for controlling the DRAM with a simple configuration. It has the effect of being able to.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram of each part thereof, and Fig. 3 is a DR using the circuit shown in Fig. 1.
FIG. 3 is a circuit diagram for controlling AM. 1 to 3...gate circuit, 4 to 6...memory circuit,
20...DRAM control circuit, 21.CPU, 22.
23...Driver 24...DRAM.

Claims (1)

[Claims] A first memory circuit that captures an input signal using a first clock signal; and a second memory circuit that captures an output signal of the first memory circuit using a second clock signal having a phase opposite to that of the first clock signal. Second
A DRAM control circuit comprising: a memory circuit; and a third memory circuit that takes in an output signal of the second memory circuit in response to a second clock signal.