JPH0358378A - Dram control circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements and to simplify an operation by providing the generation functions of RAS (row address strobe) and CAS (column address strobe) corresponding to refresh operations by CAS and RAS modes. CONSTITUTION:When a refresh request signal REF goes to 0, the CAS goes to 0, and the RAS goes to 0 after the delay time T1 of the element 2. Further more, the CAS goes to 1 after the delay time T2 of the element 3. Next, when the signal REF goes to 1, the RAS goes to 1. Such operation is the refresh operation by a CAS before RAS mode, which dispenses with the input of a refresh address to a DRAM. Thus, by providing the generation functions of RAS and CAS corresponding to the refresh operation by the CAS before RAS mode, a DRAM control circuit with a few number of elements and with simple operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a storage device using DRAM.

Prior Art FIG. 3 shows a part of a conventional DRAM control circuit. In Figure 3, MWTC is a write request signal, MR
DC is a read request signal, REF refresh request signal, SEL is a selection signal, RAS and CAS are each DRA
Row address strobe signal and column address strobe signal to M, all signals are active "o". 21, 25, and 26 are OR gates, 24 are D-type flip-flops, 27 and 28 are NAND gates, and 22 and 23 are delay elements.

Next, the operation of this circuit will be explained using FIG.

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3, ignoring signal delays caused by gates and seven resobflops. The upper row of each signal indicates "1", and the lower row indicates "○".

When SEL is already “o”, MW T C (!:
If either MRDC becomes “0”, RAS becomes “0”.
”, and CAS after T1 becomes “○”. Furthermore, RAS after T2 becomes “1”. T1 and T2 are the delay times of delay elements 22 and 23, respectively. Next, MWTC and MRDC
When both become "1", CAS becomes "1".

Correspondingly, when REF is “0”, RAS is also “0”.
” becomes.

Problems to be Solved by the Invention However, in the above conventional method, RAS and CAS are generated without using external timing signals.
Since refresh is performed in RAS-only mode, there are the following drawbacks.

When refreshing in RAS-only mode,
A refresh address must be input to the DRAM. Therefore, the DRAM control circuit is required to have a function of generating a refresh address and a function of switching between an address during a read/write operation and a refresh address. In order to satisfy these functions, the overall DRAM control circuit requires a large number of elements and its operation becomes complicated.

The present invention solves these conventional problems,
The object of the present invention is to realize a DRAM control circuit with a small number of elements and simple operation.

Means for Solving the Problems In order to achieve the above objects, a DRAM control circuit of the present invention includes two delay elements, a sequential circuit, and a combinational circuit.
Read/write operations and CAS before RAS
RAS-CA corresponding to refresh operation depending on mode
It is equipped with a S generation function.

Operation With the above configuration, the DRAM control circuit of the present invention performs the refresh operation in the CAS-be-core RAS mode, so it does not require a function of generating a refresh address and a function of switching between an address during a read/write operation and a refresh address. do not.

Furthermore, the timing of RAS-CAS corresponding to read/write operations and refresh is both generated based on the delay time by two delay elements.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of a DRAM control circuit in an embodiment of the present invention. In Figure 1, 1 is O
R gate, 2 and 3 are delay elements, 4 and 8 are AND gates,
6 is D type flip mouth horn, 6, 7, 1o, 11
is a NAND gate, and 9/12 is a NOR gate. M
WTC is a write request signal, MRDC is a read request signal,
REF is a refresh request signal, SEL is a selection signal, R
AS and CAS each provide a row address to DRAM.
The strobe signal and column strobe signal are the same, and all signals are active "0".

Next, the operation of this circuit will be explained using FIG.

FIG. 2 is a timing chart showing the operation of the circuit in FIG. 1, ignoring signal delays caused by gates and flip-flops. The upper row of each signal indicates "1", and the lower row indicates "0".

When SEL is already “0” and either MWTC or MRDC becomes “0”, RAS becomes “0”.
After 1, CAS becomes "0".

Furthermore, RAS becomes "1" after T2. T1 and T2 are the delay times of delay elements 2 and 3, respectively. Next MWTC
When both of and MRDC become "1", CAS becomes "1". The above operations are the same as those of the conventional example shown in FIG.

When REF becomes "0", CAS becomes "0", and after T1 RAS becomes "0". Furthermore, after T2, CAS becomes "1". Next, when REF becomes "1", RAS becomes "1". This operation is a refresh operation in the CAS before RAS mode, and the refresh address is input to the DRAM. There is no need to do so.

Effects of the Invention As described above, the present invention provides CAS before RAS
RAS/CA corresponding to refresh operation depending on mode
By providing the SO generation function, it is possible to realize a simple and excellent DRAM control circuit with fewer elements and operation.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a part of a DRAM control circuit according to an embodiment of the present invention, Figure 2 is a timing diagram showing the operation of the circuit in Figure 1, and Figure 3 is a diagram of a conventional DRAM control circuit. FIG. 4 is a partial circuit diagram, and FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3. 1 ・21 ・25・26・・・OR gate, 2
・3・22・23・・・Delay element, 4・8・・・・
・・AND gate, 6・24・・・・D type flip 7 lop, 6・7 10・11・2γ・28・・
...NAND gate, 9 12...NOR
Gate.

Claims (1)

[Claims] A memory device using DRAM is composed of a delay element, a sequential circuit, and a combinational circuit.
) and column address strobe (CAS) timing generation.
re) A DRAM control circuit characterized in that it is also used to generate timings for the RAS and the CAS corresponding to a refresh operation in RAS mode.