JPH06110775A - Memory controller - Google Patents

Abstract

PURPOSE:To make an output timing versatile by optionally selecting two kinds of output timings with respect to a position address timing signal and a word address timing signal. CONSTITUTION:The signal of a second timing signal generation circuit 5 is longer than the position address timing signal of a first timing signal generation circuit 4. Thus, the position address timing signal of the first timing signal generation circuit 4 is used in the case of the data buffer 3 of a short delay time and the signal of the second timing signal generation circuit 5 is used in the case of the data buffer 3 of the long delay time. Then, in accordance with a selection signal from an instruction circuit 7, a selection circuit 6 selects the position address timing signal from the first timing signal generation circuit 4, the word address timing signal or the signal from the second timing signal generation circuit 5 so as to output it to a random access memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for controlling writing or reading of data with respect to a random access memory by using a digit address timing signal and a word address timing signal.

[0002]

2. Description of the Related Art Conventionally, in a random access memory, its read data is stored and held in a data buffer.

The memory access time of the memory controller for the random access memory, that is, the output timing of the digit address timing signal and the word address timing signal, is fixed.

Therefore, when the delay time of the data buffer in which the read data from the random access memory is stored and held is changed, the memory access device is recreated to have a different memory access time, namely, The digit address timing signal and the word address timing signal had to be changed to have different output timings.

[0005]

SUMMARY OF THE INVENTION The present invention eliminates the disadvantage that the output timing of the digit address timing signal and the word address timing signal is not versatile as described above. An object of the present invention is to provide a memory control device having versatility in the output timing of a timing signal.

[0006]

A memory control device of the present invention controls writing or reading of data to or from a dynamic random access memory in which data is stored, and a digit address timing signal and a word address timing signal. First generating means for generating
Second generation means for generating a digit address timing signal and a word address timing signal at a timing different from the generation timing of the first generation means, the signal from the first generation means is used, or the second generation means is used. Instructing means for instructing whether to use the signal from the generating means, or outputting the signal from the first generating means or the signal from the second generating means in accordance with the instruction of the instructing means. Output means and a processing means for writing or reading data to or from the random access memory in response to a signal from the output means.

[0007]

According to the present invention, the digit address timing signal and the word address timing signal are controlled by the first and second digit address timing signals in the above configuration for controlling the writing or reading of data to or from the dynamic random access memory in which data is stored. Of the first generating means, the digit address timing signal and the word address timing signal are generated by the second generating means at a timing different from that of the first generating means. The instructing means indicates whether to use the signal or the signal from the second generating means, and in accordance with this instruction, the first
The signal from the generator or the signal from the second generator is output, and data is written to or read from the random access memory according to the output signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory control device of the present invention. That is, it is composed of a memory control circuit 1, a dynamic random access memory (DRAM) 2, and a data buffer 3.

The memory control circuit 1 outputs addresses, data, and control signals supplied from an external control circuit (not shown) to the random access memory 2 and digit address timing signals (CAS timing) for two types of output timing. Signal; column address select timing signal) and word address timing signal (RA
S timing signal; row address select timing signal).

As shown in FIG. 1, the memory control circuit 1 has a first timing signal generation circuit 4, a second timing signal generation circuit 5, a selection circuit 6, and an instruction circuit 7. These circuits are formed on the same substrate 8, for example. The first timing signal generation circuit 4 outputs a digit address timing signal and a word address timing signal as shown in FIGS. 2 (a) and 2 (b). The second timing signal generation circuit 5 outputs a digit address timing signal and a word address timing signal as shown in FIGS. 3 (a) and 3 (b).

The word address timing signal includes first and second word address timing signals.
The same signal is output by the timing signal generating circuits 4 and 5 and different digit address timing signals are output by the first and second timing signal generating circuits 4 and 5.

That is, the digit address timing signal of the second timing signal generating circuit 5 is longer than the digit address timing signal of the first timing signal generating circuit 4. As a result, the digit address timing signal of the first timing signal generating circuit 4 is used in the case of the data buffer 3 having a short delay time, and the digit address timing signal of the second timing signal generating circuit 5 has a long delay time. It is used in the case of the data buffer 3.

The instruction circuit 7 is configured to be selectively fixed at a high level or a low level on the substrate 8 or outputs a selection signal (high level or low level) by a DIP switch. May be. For example, when it is at a high level, it is used as a selection signal for the first timing signal generation circuit 4, and when it is at a low level, it is used as a selection signal for the second timing signal generation circuit 5. The instruction circuit 7 is
The instruction may be determined by a signal supplied to an external select pin (not shown).

The selection circuit 6 receives the digit address timing signal and the word address timing signal from the first timing signal generation circuit 4 or the second timing signal generation circuit 5 according to the selection signal from the instruction circuit 7. The digit address timing signal and the word address timing signal are selectively output. Next, the operation in such a configuration will be described.

That is, when the data buffer 3 having a long delay time is used, the output from the instruction circuit 7 is set to the low level. This low-level selection signal is output to the selection circuit 6. As a result, the selection circuit 6 operates as shown in FIG.
The digit address timing signal and the word address timing signal from the second timing signal generating circuit 5 shown in (a) and (b) are output to the random access memory 2.
Addresses, data, and control signals supplied from an external control circuit (not shown) are output to the random access memory 2 via the memory control circuit 1.

Therefore, the data from the predetermined address of the random access memory 2 is read according to the digit address timing signal and the word address timing signal from the second timing signal generating circuit 5 and supplied to the data buffer 3. , Remembered.

When the data buffer 3 having a short delay time is used, the output from the instruction circuit 7 is set to the high level. This high-level selection signal is output to the selection circuit 6. As a result, the selection circuit 6 outputs the digit address timing signal and the word address timing signal from the first timing signal generation circuit 4 shown in (a) and (b) of FIG. 2 to the random access memory 2. Addresses, data, and control signals supplied from an external control circuit (not shown) are output to the random access memory 2 via the memory control circuit 1.

Therefore, the data from the predetermined address of the random access memory 2 is read according to the digit address timing signal and the word address timing signal from the first timing signal generating circuit 4 and supplied to the data buffer 3. , Remembered.

As described above, the two kinds of output timings for the digit address timing signal and the word address timing signal are arbitrarily selected according to the delay time of the data buffer and the difference in the number of stages. For example, two types of word address timing signals having different lengths are prepared and arbitrarily selected.

Thus, the output timing of the digit address timing signal and the word address timing signal is versatile. Therefore, even if the delay time of the data buffer is changed, one memory control device can be effectively used. Further, by controlling the length of the digit address timing signal, it is possible to change the access time when reading the memory.

[0021]

As described above in detail, according to the present invention,
It is possible to provide a memory control device having versatility in the output timing of the digit address timing signal and the word address timing signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a memory control device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a timing signal generated by the first timing signal generation circuit of FIG.

3 is a timing chart for explaining a timing signal generated by a second timing signal generation circuit of FIG.

[Explanation of symbols]

1 ... Memory control circuit, 2 ... Random access memory (D
RAM), 3 ... Data buffer, 4 ... First timing signal generating circuit, 5 ... Second timing signal generating circuit, 6
... selection circuit, 7 ... instruction circuit, 8 ... substrate.

Claims (1)

[Claims] 1. A memory control device for controlling writing or reading of data to or from a dynamic random access memory in which data is stored, comprising first generating means for generating a digit address timing signal and a word address timing signal. The second generation means for generating the digit address timing signal and the word address timing signal at a timing different from the generation timing of the first generation means and the signal from the first generation means are used, or And an instruction means for instructing whether to use the signal from the second generation means, and outputting the signal from the first generation means or a signal from the second generation means according to the instruction of the instruction means. For outputting data to the random access memory according to a signal from the output means. Or a memory controller, characterized by comprising processing means for reading, a.