JPH0467753U - - Google Patents
Info
- Publication number
- JPH0467753U JPH0467753U JP10778690U JP10778690U JPH0467753U JP H0467753 U JPH0467753 U JP H0467753U JP 10778690 U JP10778690 U JP 10778690U JP 10778690 U JP10778690 U JP 10778690U JP H0467753 U JPH0467753 U JP H0467753U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- memory
- written
- odd number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第1図は本考案に係るメモリバツクアツプ回路
の構成図、第2図はバツクアツプ時の動作を示す
フローチヤート、第3図は復帰時の動作を示すフ
ローチヤートである。
1……メモリバツクアツプ回路、2……演算回
路、3……書込み回路、4……メモリ、5……読
出し回路、6……逆演算回路、7……多数決回路
、j,k,m……演算、j′,k′,m′……逆
演算、U,V,W……アドレス。
FIG. 1 is a block diagram of a memory backup circuit according to the present invention, FIG. 2 is a flowchart showing operations during backup, and FIG. 3 is a flowchart showing operations during recovery. DESCRIPTION OF SYMBOLS 1...Memory backup circuit, 2...Arithmetic circuit, 3...Write circuit, 4...Memory, 5...Readout circuit, 6...Inverse arithmetic circuit, 7...Majority circuit, j, k, m... ...Operation, j', k', m'... Inverse operation, U, V, W... Address.
Claims (1)
モリをバツクアツプするメモリバツクアツプ回路
において、このメモリに書込むデータを奇数個の
夫々異なるデータに演算する演算回路と、この夫
々異なるデータをこのメモリの隣接アドレスを除
くアドレスに書込む書込み回路と、この夫々書込
まれたデータを読出す読出し回路と、この読出し
たデータを元のデータに戻すためにこのデータを
逆演算する逆演算回路と、この逆演算した奇数個
のデータを夫々比較して同一データを多数決で1
つ選択する多数決回路とを備えたことを特徴とす
るメモリバツクアツプ回路。 A memory backup circuit that backs up a memory in which data can be written or read electrically includes an arithmetic circuit that calculates the data to be written into the memory into an odd number of different data, and an arithmetic circuit that converts the data to be written into the memory into an odd number of different data, and an arithmetic circuit that converts the data to be written into the memory into an odd number of different data. A write circuit that writes to addresses other than addresses, a read circuit that reads each written data, an inverse calculation circuit that performs an inverse operation on this read data to return it to the original data, and Compare the calculated odd number of data and select the same data as 1 by majority vote.
1. A memory backup circuit comprising: a majority circuit for selecting one.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10778690U JPH0467753U (en) | 1990-10-15 | 1990-10-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10778690U JPH0467753U (en) | 1990-10-15 | 1990-10-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0467753U true JPH0467753U (en) | 1992-06-16 |
Family
ID=31854466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10778690U Pending JPH0467753U (en) | 1990-10-15 | 1990-10-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0467753U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6170637A (en) * | 1984-09-11 | 1986-04-11 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Correction of error detection due to decision by majority |
JPS63163650A (en) * | 1986-12-26 | 1988-07-07 | Matsushita Electric Ind Co Ltd | Ic card |
-
1990
- 1990-10-15 JP JP10778690U patent/JPH0467753U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6170637A (en) * | 1984-09-11 | 1986-04-11 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Correction of error detection due to decision by majority |
JPS63163650A (en) * | 1986-12-26 | 1988-07-07 | Matsushita Electric Ind Co Ltd | Ic card |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0467753U (en) | ||
JPS60104944U (en) | Image data processing device | |
JPS63199347U (en) | ||
JPH0482735U (en) | ||
JPH0397703U (en) | ||
JPH02149165U (en) | ||
JPH029940U (en) | ||
JPS58138142U (en) | display device | |
JPS5958843U (en) | Random access memory initialization circuit | |
JPS59108941U (en) | Parity check circuit | |
JPS6047695U (en) | Pusher-ship linkage device | |
JPS6348247U (en) | ||
JPS59192755U (en) | Elastic store circuit | |
JPH0397746U (en) | ||
JPH0184152U (en) | ||
JPS63199345U (en) | ||
JPS62199859U (en) | ||
JPS6121542A (en) | Data transfer device | |
JPH0223138U (en) | ||
JPS60166899U (en) | Storage device | |
JPH0298557U (en) | ||
JPS6438000U (en) | ||
JPH01155542U (en) | ||
JPH0466645U (en) | ||
JPH0270249U (en) |