JPH0466645U - - Google Patents
Info
- Publication number
- JPH0466645U JPH0466645U JP10389190U JP10389190U JPH0466645U JP H0466645 U JPH0466645 U JP H0466645U JP 10389190 U JP10389190 U JP 10389190U JP 10389190 U JP10389190 U JP 10389190U JP H0466645 U JPH0466645 U JP H0466645U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- error
- data
- bits
- processed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Description
第1図は本考案による2つのパリテイビツトを
用いた誤り検出回路の実施例を示す回路ブロツク
図、第2図は従来のパリテイチエツク方式を実現
する回路図である。
1,10……制御部(CPU)、2,3,11
……パリテイジエネレータ、4,5,14……比
較回路、6,12……8ビツト幅メモリ、7……
偶数パリテイビツト用メモリ、8……奇数パリテ
イビツト用メモリ、9……メモリエラー判定回路
。
FIG. 1 is a circuit block diagram showing an embodiment of an error detection circuit using two parity bits according to the present invention, and FIG. 2 is a circuit diagram realizing a conventional parity check method. 1, 10...Control unit (CPU), 2, 3, 11
... Parity generator, 4, 5, 14 ... Comparison circuit, 6, 12 ... 8-bit width memory, 7 ...
Memory for even parity bits, 8...Memory for odd parity bits, 9...Memory error determination circuit.
Claims (1)
記憶する場合、2つのパリテイビツトを付加し、
前記データと第1のパリテイビツトでは偶数パリ
テイに、前記データと第2のパリテイでは奇数パ
リテイになるように処理し、前記メモリより続出
す場合、前記偶数および奇数パリテイチエツクを
行い、前記偶数または奇数パリテイチエツクの一
方にのみ誤りを検出したときは、パリ自体の誤り
と判定して動作を継続させ、前記両方に誤りを検
出したときは、データに誤りがあると判定するよ
うに構成したことを特徴とする2つのパリテイブ
ツトを用いた誤り検出回路。 When storing data consisting of multiple bits in memory, add two parity bits,
The data and the first parity bits are processed to have an even parity, and the data and the second parity bits are processed to be an odd parity. When the data is continuously output from the memory, the even and odd parity checks are performed, and the even and odd parity bits are processed. When an error is detected in only one of the parity checks, it is determined that the error is in the parity itself, and the operation continues, and when an error is detected in both of the above, it is determined that there is an error in the data. An error detection circuit using two parity chips characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10389190U JPH0466645U (en) | 1990-10-02 | 1990-10-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10389190U JPH0466645U (en) | 1990-10-02 | 1990-10-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0466645U true JPH0466645U (en) | 1992-06-12 |
Family
ID=31848939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10389190U Pending JPH0466645U (en) | 1990-10-02 | 1990-10-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0466645U (en) |
-
1990
- 1990-10-02 JP JP10389190U patent/JPH0466645U/ja active Pending
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