JPH0467730U - - Google Patents
Info
- Publication number
- JPH0467730U JPH0467730U JP11068090U JP11068090U JPH0467730U JP H0467730 U JPH0467730 U JP H0467730U JP 11068090 U JP11068090 U JP 11068090U JP 11068090 U JP11068090 U JP 11068090U JP H0467730 U JPH0467730 U JP H0467730U
- Authority
- JP
- Japan
- Prior art keywords
- board
- rom
- cpu
- main board
- microcomputer device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案に係るマイクロコンピユータ装
置の第１の実施例の構成図、第２図は本考案に係
るマイクロコンピユータ装置の第２の実施例の構
成図、第３図は本考案に係るマイクロコンピユー
タ装置の第３の実施例の構成図、第４図は従来の
マイクロコンピユータ装置の構成図である。
１，２１……主基板、２，２２……ＲＯＭ基板
、３，２３……ＣＰＵ、４，２４……クロツク発
生回路、５，２５……ＲＡＭ及びＲＡＭ制御部、
６，２６……ＣＰＵ周辺回路、７，２７……キヤ
ラクタジエネレータ用ＲＯＭ、８，２８……Ｉ／
Ｏ制御回路、９，２９……ＲＯＭ、１０，３０…
…チツプセレクト回路、１１，３１……アドレス
バス、１２，３２……データバス、１３，３３…
…制御バス、３４……クロツク信号線、ＣＬＫ…
…クロツク信号。
FIG. 1 is a block diagram of a first embodiment of a microcomputer device according to the present invention, FIG. 2 is a block diagram of a second embodiment of a microcomputer device according to the present invention, and FIG. 3 is a block diagram of a second embodiment of a microcomputer device according to the present invention. FIG. 4 is a block diagram of a third embodiment of a microcomputer device, and FIG. 4 is a block diagram of a conventional microcomputer device. 1, 21... Main board, 2, 22... ROM board, 3, 23... CPU, 4, 24... Clock generation circuit, 5, 25... RAM and RAM control unit,
6, 26... CPU peripheral circuit, 7, 27... ROM for character generator, 8, 28... I/
O control circuit, 9, 29...ROM, 10, 30...
...Chip select circuit, 11,31...Address bus, 12,32...Data bus, 13,33...
...Control bus, 34...Clock signal line, CLK...
...clock signal.
Claims (1)
れている主基板と、主基板から分離独立したＲＯ
Ｍ基板とを有し、前記ＲＯＭ基板には、フオント
データを発生するキヤラクタジエネレータ用ＲＯ
Ｍと、ＣＰＵの制御プログラムを格納しているＲ
ＯＭとが搭載されていることを特徴とするマイク
ロコンピユータ装置。 ２ 複数のユニツトが搭載されている主基板と、
主基板から分離独立したＲＯＭ基板とを有し、前
記ＲＯＭ基板には、全体の制御を行なうＣＰＵと
、ＣＰＵの制御プログラムを格納しているＲＯＭ
とが搭載されていることを特徴とするマイクロコ
ンピユータ装置。 ３ 請求項２記載のマイクロコンピユータ装置に
おいて、前記ＲＯＭ基板にはさらにクロツク発生
回路が搭載されていることを特徴とするマイクロ
コンピユータ装置。[Claims for Utility Model Registration] 1. A main board on which multiple units including a CPU are mounted, and an RO that is separate and independent from the main board.
M board, and the ROM board has an RO for a character generator that generates font data.
M, and R that stores the CPU control program.
A microcomputer device characterized by being equipped with an OM. 2 A main board on which multiple units are mounted,
It has a ROM board that is separate and independent from the main board, and the ROM board includes a CPU that performs overall control and a ROM that stores a control program for the CPU.
A microcomputer device characterized by being equipped with. 3. The microcomputer device according to claim 2, wherein the ROM board further includes a clock generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11068090U JPH0467730U (en) | 1990-10-23 | 1990-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11068090U JPH0467730U (en) | 1990-10-23 | 1990-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467730U true JPH0467730U (en) | 1992-06-16 |
Family
ID=31858059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11068090U Pending JPH0467730U (en) | 1990-10-23 | 1990-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467730U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122276A (en) * | 1984-07-10 | 1986-01-30 | Nec Corp | Altitude depth sonar |
| JPH03147392A (en) * | 1989-10-23 | 1991-06-24 | Internatl Business Mach Corp <Ibm> | Personal computer system unit and processor card |
-
1990
- 1990-10-23 JP JP11068090U patent/JPH0467730U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122276A (en) * | 1984-07-10 | 1986-01-30 | Nec Corp | Altitude depth sonar |
| JPH03147392A (en) * | 1989-10-23 | 1991-06-24 | Internatl Business Mach Corp <Ibm> | Personal computer system unit and processor card |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0467730U (en) | ||
| JPS5326632A (en) | Common memory control unit | |
| JPH03113453U (en) | ||
| JPH02143603U (en) | ||
| JPH0179164U (en) | ||
| JPH0393971U (en) | ||
| JPS5889450U (en) | work machine | |
| JPS6356449U (en) | ||
| JPS62175352U (en) | ||
| JPS6452066U (en) | ||
| JPH0227355U (en) | ||
| JPS6057888U (en) | cash register machine | |
| JPH01107166U (en) | ||
| JPH03123292U (en) | ||
| JPS6361026U (en) | ||
| JPH0276397U (en) | ||
| JPH0445086U (en) | ||
| JPS61196350U (en) | ||
| JPH0466646U (en) | ||
| JPH0397710U (en) | ||
| JPS62195863U (en) | ||
| JPS6353152U (en) | ||
| JPH0399387U (en) | ||
| JPH0397746U (en) | ||
| JPS6251428U (en) |