JPH0458754B2 - - Google Patents

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Publication number
JPH0458754B2
JPH0458754B2 JP28978585A JP28978585A JPH0458754B2 JP H0458754 B2 JPH0458754 B2 JP H0458754B2 JP 28978585 A JP28978585 A JP 28978585A JP 28978585 A JP28978585 A JP 28978585A JP H0458754 B2 JPH0458754 B2 JP H0458754B2
Authority
JP
Japan
Prior art keywords
circuit
frequency
output
signal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP28978585A
Other languages
Japanese (ja)
Other versions
JPS62147875A (en
Inventor
Kenji Ooe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP28978585A priority Critical patent/JPS62147875A/en
Publication of JPS62147875A publication Critical patent/JPS62147875A/en
Publication of JPH0458754B2 publication Critical patent/JPH0458754B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はYIG(Yttrium Iron Garnet)フイル
タに所要値電流を供給してその周波数選択特性の
周波数分布を設定するYIGフイルタの駆動回路に
関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a YIG (Yttrium Iron Garnet) filter that supplies a required value of current to a YIG (Yttrium Iron Garnet) filter to set the frequency distribution of its frequency selection characteristics.

(従来の技術) 第6図は従来のYIGフイルタの駆動回路を用い
た受信機を示し、この受信機は入力端子1に入力
される高周波信号に含まれる各種周波数範囲の信
号の中の1つをYIGフイルタ2によつて選別し、
これを中間周波回路6を介してビデオ回路7で検
波し、出力端子8からビデオ信号を得るものであ
る。ここで、YIGフイルタ2の周波数選別動作
は、電圧発生回路3、電圧選択回路4、および電
圧−電流変換回路5で構成される駆動回路10の
指令によつて行なわれる。
(Prior Art) FIG. 6 shows a receiver using a conventional YIG filter drive circuit. are sorted by YIG filter 2,
This signal is detected by a video circuit 7 via an intermediate frequency circuit 6, and a video signal is obtained from an output terminal 8. Here, the frequency selection operation of the YIG filter 2 is performed in response to a command from a drive circuit 10 composed of a voltage generation circuit 3, a voltage selection circuit 4, and a voltage-current conversion circuit 5.

電圧発生回路3は例えば3種の電圧V1、同V2
同V3を発生し、夫々を電圧選択回路4へ出力す
る。電圧選択回路4は入力された3種の電圧V1
同V2、同V3の中の1つの電圧を選択して電圧−
電流変換回路5へ出力する。
The voltage generation circuit 3 generates, for example, three types of voltages V 1 , V 2 ,
The voltage selection circuit 4 generates the voltage V 3 and outputs each voltage to the voltage selection circuit 4. The voltage selection circuit 4 selects three types of input voltages V 1 ,
Select one voltage from V 2 and V 3 and set the voltage -
Output to current conversion circuit 5.

電圧−電流変換回路5は入力電圧に比例した電
流をYIGフイルタ2へ供給する。
The voltage-current conversion circuit 5 supplies a current proportional to the input voltage to the YIG filter 2.

その結果、YIGフイルタ2の周波数選択特性が
決定される。例えば、第7図ロに示す如く、YIG
フイルタ2は周波数選択特性の周波数分布の帯域
幅がΔfsの帯域通過フイルタであるが、印加電流
値に対応する電圧値が電圧V1、同V2、同V3と変
化すると、帯域幅Δfsの中心周波数が周波数f1
同f2、同f3と変化する。
As a result, the frequency selection characteristics of the YIG filter 2 are determined. For example, as shown in Figure 7B, YIG
Filter 2 is a bandpass filter whose frequency distribution has a bandwidth of Δfs, but when the voltage value corresponding to the applied current value changes to voltage V 1 , V 2 , and V 3 , the bandwidth Δfs changes. The center frequency is the frequency f 1 ,
It changes to f 2 and f 3 .

このようなYIGフイルタ2に対し、入力する高
周波信号は、第7図イに示す如く、周波数f1、同
f2、同f3を中心周波数とし、周波数分布の帯域幅
が夫々Δf(Δf<Δfs)である3個の信号からなる
とする。今、電圧選択回路4が電圧V1を選択し
たとすると、YIGフイルタ2は周波数f1を中心周
波数とするから、高周波信号は中心周波数f1の信
号が選択されることになる(第7図ハ))。
The input high frequency signal to such a YIG filter 2 has a frequency f 1 and a same frequency as shown in FIG. 7A.
It is assumed that the signal consists of three signals whose center frequencies are f 2 and f 3 and whose frequency distribution bandwidths are Δf (Δf<Δfs). Now, if the voltage selection circuit 4 selects the voltage V 1 , the YIG filter 2 has the frequency f 1 as its center frequency, so the signal with the center frequency f 1 is selected as the high frequency signal (see Figure 7). Ha)).

(発明が解決しようとする問題点) ところで、この種のYIGフイルタおよびその駆
動回路が広い温度変化範囲で使用され、電圧発生
回路3で作られる電圧V1、同V2および同V3の温
度変化による変動や、電圧−電流変換回路5の温
度変化による出力電流のドリフト、さらにはYIG
フイルタ2自体の温度変化による周波数選択特性
の変化があると、選別周波数の中心周波数が例え
ば第8図ロに示すようにf1からf1+fuにずれてし
まい、その結果YIGフイルタ2から出力される信
号の周波数分布は、第8図ハに示すように、入力
された高周波信号の周波数分布(第8図イ))と
異なり、帯域幅Δfの一部分が欠如した周波数分
布となるという問題点がある。
(Problems to be Solved by the Invention) By the way, this type of YIG filter and its drive circuit are used in a wide temperature change range, and the temperature of the voltages V 1 , V 2 and V 3 generated by the voltage generation circuit 3 fluctuations due to changes in the output current, drifts in the output current due to temperature changes in the voltage-current converter circuit 5, and even YIG
If the frequency selection characteristics of the filter 2 itself change due to temperature changes, the center frequency of the screening frequency will shift from f 1 to f 1 +fu, for example, as shown in Figure 8B, and as a result, the YIG filter 2 will output As shown in Figure 8C, the frequency distribution of the input signal differs from the frequency distribution of the input high-frequency signal (Figure 8B)), and there is a problem in that the frequency distribution lacks a portion of the bandwidth Δf. be.

本発明の目的は広い範囲で温度変化があつても
YIGフイルタの周波数選択特性に変動が生じない
ようにすることが出来るYIGフイルタの駆動回路
を提供することにある。
The purpose of the present invention is to
An object of the present invention is to provide a drive circuit for a YIG filter that can prevent fluctuations in the frequency selection characteristics of the YIG filter.

(問題点を解決するための手段) 上記目的を達成するために本発明に係るYIGフ
イルタの駆動回路は次の如き構成を有する。
(Means for Solving the Problems) In order to achieve the above object, a YIG filter drive circuit according to the present invention has the following configuration.

即ち、本発明に係るYIGフイルタの駆動回路
は、YIGフイルタに所要値電流を供給しその周波
数選択特性のの周波数分布を設定するYIGフイル
タの駆動回路であつて、前記YIGフイルタの前記
周波数分布の高域遮断周波数および低域遮断周波
数に近接し、かつ該周波数分布の外側に適宜周波
数だけ離隔した周波数の信号である上限しきい値
周波数信号および下限しきい値周波数信号を発生
するしきい値周波数信号発生器と;前記上限しき
い値周波数信号と下限しきい値周波数信号を受け
て両者を交互に切り換えて出力する上限下限切換
回路と;一定の繰返し周波数で繰り返され所定周
波数分布を有する高周波信号を一方の入力とし、
前記上限下限切換回路の出力を他方の入力とし、
両入力を交互に切換えて前記YIGフイルタに出力
するものであつて、高周波信号の前記繰返し周期
内の所定の一部時間において他方の入力を選択す
るフイルタ入力切換回路と;前記YIGフイルタの
出力を受けてそれをビデオ信号に変換するビデオ
回路と;前記ビデオ信号を受けてそれを反転増幅
する反転増幅器と;前記上限下限切換回路の切換
動作に同期して前記反転増幅器の出力と前記ビデ
オ回路の出力を交互に切り換えて出力する極性切
換回路と;所要の積分動作を行なう積分回路と;
前記フイルタ切換回路の切換動作に同期して前記
積分回路の出力と前記極性切換回路の出力とを交
互に切り換えて前記積分回路へ出力する積分入力
切換回路と;前記YIGフイルタの周波数選択特性
を規定すべく所要値の電圧を発生する電圧発生回
路と;前記電圧発生回路が発生する電圧と前記積
分回路の出力とを受けて両入力値を加算した所要
値電圧を出力する加算器と;前記加算器の出力電
圧を受けて前記YIGフイルタへ前記所要値電流の
供給を行なう電圧−電流変換回路と;を備えてい
ることを特徴とする。
That is, the YIG filter drive circuit according to the present invention is a YIG filter drive circuit that supplies a required current to the YIG filter and sets the frequency distribution of its frequency selection characteristic. Threshold frequency that generates an upper threshold frequency signal and a lower threshold frequency signal, which are signals with frequencies close to the high cutoff frequency and the low cutoff frequency, and separated by an appropriate frequency outside the frequency distribution. a signal generator; an upper and lower limit switching circuit that receives the upper limit threshold frequency signal and the lower limit threshold frequency signal and alternately switches and outputs both; a high frequency signal that is repeated at a constant repetition frequency and has a predetermined frequency distribution; As one input,
The output of the upper and lower limit switching circuit is used as the other input,
a filter input switching circuit that alternately switches both inputs and outputs them to the YIG filter, and selects the other input at a predetermined part of time within the repetition period of the high frequency signal; a video circuit that receives the video signal and converts it into a video signal; an inverting amplifier that receives the video signal and inverts and amplifies it; and an output of the inverting amplifier and the output of the video circuit in synchronization with the switching operation of the upper/lower limit switching circuit. A polarity switching circuit that alternately switches and outputs the output; An integrating circuit that performs the required integral operation;
an integral input switching circuit that alternately switches between the output of the integrating circuit and the output of the polarity switching circuit and outputs the output to the integrating circuit in synchronization with the switching operation of the filter switching circuit; defining frequency selection characteristics of the YIG filter; a voltage generating circuit that generates a voltage of a required value to be output; an adder that receives the voltage generated by the voltage generating circuit and the output of the integrating circuit and outputs a required voltage that is the sum of both input values; and a voltage-current conversion circuit that receives the output voltage of the filter and supplies the required current to the YIG filter.

(作用) 次に、前記の如き構成を有するYIGフイルタの
駆動回路の作用を説明する。なお、以下の説明で
はYIGフイルタは印加電流値が増加すると、その
周波数選択特性の周波数分布は高域側に移行し、
印加電流値が減少すると逆に低域側に移行するも
のとする。また、ビデオ回路に含まれる検波用ダ
イオードは正極性検波を行なうものとする。
(Operation) Next, the operation of the YIG filter drive circuit having the above configuration will be explained. In addition, in the following explanation, as the applied current value increases, the frequency distribution of the YIG filter's frequency selection characteristics shifts to the higher frequency side.
It is assumed that when the applied current value decreases, it shifts to the lower frequency side. Further, it is assumed that the detection diode included in the video circuit performs positive polarity detection.

YIGフイルタは所要値電流の供給を受けてその
周波数選択特性の周波数分布が設定されるが、こ
の所要値電流の供給は本来電圧発生回路が発生す
る所要値電圧に基づき行なわれるが、本発明にお
いては次の如くしてこの所要値電圧に温度変化に
基づく修正が加えられる。
The frequency distribution of the frequency selection characteristic of the YIG filter is set by receiving the required value current. Originally, this required value current is supplied based on the required value voltage generated by the voltage generating circuit, but in the present invention, The required value voltage is corrected based on the temperature change as follows.

即ち、しきい値周波数信号発生器が発生する上
限しきい値周波数信号および下限しきい値周波数
信号は上限下限切換回路によつて交互に切換えら
れてフイルタ入力切換回路の他方の入力に印加さ
れる。フイルタ入力切換回路は一定の繰返し周波
数で繰り返され所定周波数分布を有する高周波信
号を一方の入力とし、前記上限下限切換回路の出
力を他方の入力とし、両入力を交互に切換えて前
記YIGフイルタに出力するものであるが、このと
き高周波信号の前記繰返し周期内の所定の一部時
間において他方の入力を選択するようにその切換
動作を行なう。即ち、温度の影響によつてYIGフ
イルタの周波数選択特性の周波数分布が例えば低
域周波数側にずれ込むと、低域遮断周波数が下限
しきい値周波数信号の周波数よりも低い方へ移る
ので、下限しきい値周波数信号がYIGフイルタの
周波数分布内に入ることになる。
That is, the upper threshold frequency signal and the lower threshold frequency signal generated by the threshold frequency signal generator are alternately switched by the upper/lower limit switching circuit and applied to the other input of the filter input switching circuit. . The filter input switching circuit takes as one input a high frequency signal that is repeated at a constant repetition frequency and has a predetermined frequency distribution, takes the output of the upper and lower limit switching circuit as the other input, and alternately switches both inputs and outputs them to the YIG filter. However, at this time, the switching operation is performed so as to select the other input at a predetermined part of time within the repetition period of the high frequency signal. In other words, if the frequency distribution of the frequency selection characteristic of the YIG filter shifts to the lower frequency side due to the influence of temperature, the lower cutoff frequency will shift to lower than the frequency of the lower limit threshold frequency signal. The threshold frequency signal will fall within the frequency distribution of the YIG filter.

その結果、YIGフイルタの出力信号は、高周波
信号のみの場合(上限下限切換回路は上限しきい
値周波数信号を選択)Aと、高周波信号と下限し
きい値周波数信号の場合(上限下限切換回路は下
限しきい値周波数信号を選択)Bとがある。
As a result, the output signal of the YIG filter is A in the case of only a high frequency signal (the upper/lower limit switching circuit selects the upper threshold frequency signal), and in the case of a high frequency signal and the lower limit threshold frequency signal (the upper/lower limit switching circuit selects the upper threshold frequency signal). There is a lower limit threshold frequency signal selection) B.

このような出力信号がビデオ回路に入力される
のである。ビデオ回路の出力は直接的に極性切換
回路へ入力されるとともに、反転増幅器を介して
極性切換回路へ入力される。極性切換回路は前記
上限下限切換回路の切換動作に同期して前記反転
増幅器の出力と前記ビデオ回路の出力を交互に切
り換えて出力する。つまり、今の場合には、前記
上限下限切換回路が上限しきい値周波数信号を選
択した時は前記反転増幅器の出力信号を選択し、
下限しきい値周波数信号を選択した時は前記ビデ
オ回路の出力信号を選択し、夫々を交互に積分入
力切換回路へ出力する。
Such an output signal is input to the video circuit. The output of the video circuit is input directly to the polarity switching circuit and also to the polarity switching circuit via an inverting amplifier. The polarity switching circuit alternately switches and outputs the output of the inverting amplifier and the output of the video circuit in synchronization with the switching operation of the upper limit/lower limit switching circuit. That is, in this case, when the upper and lower limit switching circuit selects the upper threshold frequency signal, it selects the output signal of the inverting amplifier;
When the lower limit threshold frequency signal is selected, the output signals of the video circuit are selected and each of them is alternately output to the integral input switching circuit.

次いで、積分入力切換回路は、前記フイルタ切
換回路の切換動作に同期して前記積分回路の出力
と前記極性切換回路の出力とを交互に切り換えて
前記積分回路へ出力する。つまり、今の場合に
は、積分入力切換回路は前記フイルタ入力回路と
同期した切換動作を行ない、フイルタ入力切換回
路が高周波信号を選択した時は、積分回路の出力
を選択し、フイルタ入力切換回路が前記上限下限
切換回路の出力を選択した時は前記極性切換回路
の出力を選択し、夫々を切換えて積分回路に出力
する。その結果、積分回路はビデオ回路の出力信
号が前記Bである場合の下限しきい値周波数信号
が存在する時間区間において積分動作を開始し、
その積分動作を繰り返すことによつて所要値(今
の場合には正の値である)の積分出力を加算器に
与える。加算器は該積分出力を電圧発生器が発生
する電圧に加算して電圧−電流変換回路に出力す
る。
Next, the integral input switching circuit alternately switches between the output of the integrating circuit and the output of the polarity switching circuit in synchronization with the switching operation of the filter switching circuit, and outputs the output to the integrating circuit. In other words, in this case, the integral input switching circuit performs a switching operation in synchronization with the filter input circuit, and when the filter input switching circuit selects a high frequency signal, it selects the output of the integrating circuit, and the filter input switching circuit When it selects the output of the upper/lower limit switching circuit, it selects the output of the polarity switching circuit, switches each of them, and outputs them to the integrating circuit. As a result, the integrating circuit starts an integrating operation in the time interval in which the lower limit threshold frequency signal exists when the output signal of the video circuit is B,
By repeating the integral operation, an integral output of a required value (in this case, a positive value) is provided to the adder. The adder adds the integrated output to the voltage generated by the voltage generator and outputs the result to the voltage-current conversion circuit.

これにより、電圧−電流変換回路はYIGフイル
タに対して低域側にずれた周波数分布を高域側に
移行させるべく補正する前記所要値電流を供給す
ることになる。
As a result, the voltage-current conversion circuit supplies the required current value to the YIG filter so as to correct the frequency distribution shifted to the lower frequency side to the higher frequency side.

なお、YIGフイルタの周波数選択特性の周波数
分布が高域周波数側にずれた場合には積分出力は
負の所要値となるので、上述とは逆向きの修正動
作が行なわれる。
Note that when the frequency distribution of the frequency selection characteristic of the YIG filter shifts to the higher frequency side, the integral output becomes a negative required value, so a correction operation in the opposite direction to that described above is performed.

以上の動作は繰り返し行なわれるので、YIGフ
イルタの周波数選択特性の周波数分布は温度変化
に影響されず安定的に所望の性能を維持すること
になる。
Since the above operations are repeated, the frequency distribution of the frequency selection characteristic of the YIG filter is not affected by temperature changes and stably maintains the desired performance.

このように、本発明によれば、温度変化によつ
てYIGフイルタおよびその駆動回路に変動があつ
てYIGフイルタの周波数選択特性の周波数分布が
正規の位置からずれた場合、これを自動的に補正
することができる。
As described above, according to the present invention, when the frequency distribution of the frequency selection characteristic of the YIG filter deviates from the normal position due to fluctuations in the YIG filter and its drive circuit due to temperature changes, this can be automatically corrected. can do.

(実施例) 以下、本発明を図面を参照して説明する。(Example) Hereinafter, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例に係るYIGフイルタ
の駆動回路を示す。なお、第6図と同一構成部分
には同一名称符号を付してある。
FIG. 1 shows a YIG filter drive circuit according to an embodiment of the present invention. Note that the same components as in FIG. 6 are given the same names and symbols.

このYIGフイルタの駆動回路は前記YIGフイル
タ2、電圧発生回路3、電圧選択回路4、電圧−
電流変換回路5の他、さらに制御回路102、し
きい値周波数信号発生回路103、しきい値周波
数選択回路104、上限下限切換回路105、フ
イルタ入力切換回路106、反転増幅器107、
バツフア108、同109、極性切換回路11
0、積分入力切換回路111、積分回路112、
および加算器113を備える。制御回路102は
外部から入力端子101を介して供給されるトリ
ガ信号を受けて、切換信号#1を上限下限切換回
路105と極性切換回路110へ、切換信号#2
をフイルタ入力切換回路106と積分入力切換回
路111へ夫々出力する。その結果、上限下限切
換回路105と極性切換回路110、およびフイ
ルタ入力切換回路106と積分入力切換回路11
1は夫々連動してその切換動作を行なうようにな
つている(詳細は後述する)。
The drive circuit for this YIG filter includes the YIG filter 2, voltage generation circuit 3, voltage selection circuit 4, voltage -
In addition to the current conversion circuit 5, there are also a control circuit 102, a threshold frequency signal generation circuit 103, a threshold frequency selection circuit 104, an upper/lower limit switching circuit 105, a filter input switching circuit 106, an inverting amplifier 107,
Buffer 108, buffer 109, polarity switching circuit 11
0, integral input switching circuit 111, integral circuit 112,
and an adder 113. The control circuit 102 receives a trigger signal supplied from the outside via the input terminal 101, and sends the switching signal #1 to the upper/lower limit switching circuit 105 and the polarity switching circuit 110, and passes the switching signal #2 to the upper/lower limit switching circuit 105 and the polarity switching circuit 110.
is output to the filter input switching circuit 106 and the integral input switching circuit 111, respectively. As a result, the upper/lower limit switching circuit 105, the polarity switching circuit 110, the filter input switching circuit 106, and the integral input switching circuit 11
1 are adapted to perform the switching operation in conjunction with each other (details will be described later).

しきい値周波数信号発生回路103は、複数対
のしきい値周波数信号f1L,f1Mを発生し、それを
しきい値周波数選択回路104へ送出する ここに、しきい値周波数信号f1LはYIGフイル
タ2の周波数選別特性の周波数分布の低域遮断周
波数位置より若干低く、またf1Mは高域遮断周波
数位置より若干高い周波数位置に設定される。
The threshold frequency signal generation circuit 103 generates a plurality of pairs of threshold frequency signals f 1L and f 1M and sends them to the threshold frequency selection circuit 104. Here, the threshold frequency signal f 1L is f 1M is set at a frequency position that is slightly lower than the low cutoff frequency position of the frequency distribution of the frequency selection characteristic of the YIG filter 2 and slightly higher than the high cutoff frequency position.

この実施例では、高周波信号が第2図イに示す
如く中心周波数がf1,f2およびf3である3種の信
号からなるとしているので、第2図ロに示す如く
YIGフイルタ2の周波数選別特性の周波数分布3
1、同32、同33も夫々中心周波数がf1,f2
よびf3である。
In this embodiment, it is assumed that the high frequency signal consists of three types of signals whose center frequencies are f 1 , f 2 and f 3 as shown in Fig. 2A, so as shown in Fig. 2B.
Frequency distribution 3 of frequency selection characteristics of YIG filter 2
1, 32, and 33 also have center frequencies f 1 , f 2 , and f 3 , respectively.

従つて、しきい値周波数信号f1L,f1Mは3組設
けられ、第2図ハに示す如く、f1L,f1Mは周波数
分布31に、f2L,f2Mは周波数分布32に、f3L
f3Mは周波数分布33に夫々対応している。なお、
高周波信号の帯域幅をΔf、YIGフイルタのそれ
をΔfsとすると、Δfs>Δfである。しきい値周波
数信号選択回路104は電圧選択回路4と連動し
て切換る2連のスイツチであり、電圧選択回路4
が電圧V1を選択するように設定されている場合、
しきい値周波数信号発生回路103の出力のう
ち、周波数f1Lと同f1Mの信号を選択し、電圧V2
選択するように設定されている場合、周波数f2L
と同f2Mの信号を選択し、電圧V3を選択するよう
に設定されている場合、周波数f3Lと同f3Mの信号
を選択し、夫々上限下限切換回路105へ送出す
る。上限下限切換回路105は、制御回路102
から供給される切換信号#1によつて、極性切換
回路110と連動して切換るスイツチであり、し
きい値周波数信号選択回路104から送られてく
る上限と下限のしきい値周波数信号を交互に選択
して、フイルタ入力切換回路106へ送出する。
Therefore, three sets of threshold frequency signals f 1L and f 1M are provided , and as shown in FIG. 3L ,
f 3M corresponds to the frequency distribution 33, respectively. In addition,
If the bandwidth of the high frequency signal is Δf and that of the YIG filter is Δfs, then Δfs>Δf. The threshold frequency signal selection circuit 104 is a double switch that switches in conjunction with the voltage selection circuit 4.
If is set to select voltage V 1 , then
Among the outputs of the threshold frequency signal generation circuit 103, if the signal with the same frequency f 1M as the frequency f 1L is selected and the voltage V 2 is selected, the frequency f 2L
If it is set to select a signal with a frequency f 2M and a voltage V 3 , a signal with a frequency f 3L and a signal with a frequency f 3M are selected and sent to the upper/lower limit switching circuit 105, respectively. The upper/lower limit switching circuit 105 is connected to the control circuit 102
This is a switch that is switched in conjunction with the polarity switching circuit 110 by the switching signal #1 supplied from the polarity switching circuit 110, and alternately switches between the upper limit and lower limit threshold frequency signals sent from the threshold frequency signal selection circuit 104. is selected and sent to the filter input switching circuit 106.

フイルタ入力切換回路106は制御回路102
から供給される切換信号#2によつて積分入力切
換回路111と連動して切換るスイツチであり、
高周波信号と、上限下限切換回路105から送ら
れてくる、上限又は下限のしきい値周波数信号を
時分割で切換え、YIGフイルタ2に送出する。
The filter input switching circuit 106 is connected to the control circuit 102
This is a switch that is switched in conjunction with the integral input switching circuit 111 by the switching signal #2 supplied from the
The high frequency signal and the upper limit or lower limit threshold frequency signal sent from the upper/lower limit switching circuit 105 are switched in a time-division manner and sent to the YIG filter 2.

ここで、上記各回路の動作によつてYIGフイル
タ2の入力がどのようになるかについて第3図を
参照して説明する。
Here, how the input to the YIG filter 2 changes depending on the operation of each of the circuits described above will be explained with reference to FIG.

第3図において、高周波信号は一定時間長の有
効な情報を含む時間区間(有効な区間)と、無効
な情報を含む時間区間(無効な区間)が交互に連
続する信号である(第3図ロ))。
In Fig. 3, the high-frequency signal is a signal in which a time interval containing valid information (valid interval) of a certain length of time and a time interval containing invalid information (invalid interval) alternately continue (Fig. 3). B)).

トリガ信号はこの高周波信号の有効な区間の先
頭位置に同期して制御回路102へ入力するよう
になつている(第3図イ))。つまり、制御回路1
02はこのトリガ信号101の各入力に応答して
前記切換信号#1、同#2を発生するが、上限下
限切換回路105へ供給する切換信号#1は、ト
リガ信号が入力される毎に、上限のしきい値周波
数信号f1Mと下限のしきい値周波数信号f1Lを交互
に選択するように上限下限切換回路105を制御
する信号である(第3図ニ)。
The trigger signal is input to the control circuit 102 in synchronization with the beginning position of the effective section of this high frequency signal (FIG. 3A)). In other words, control circuit 1
02 generates the switching signals #1 and #2 in response to each input of the trigger signal 101, but the switching signal #1 supplied to the upper/lower limit switching circuit 105 changes every time a trigger signal is input. This signal controls the upper/lower limit switching circuit 105 to alternately select the upper limit threshold frequency signal f 1M and the lower limit threshold frequency signal f 1L (FIG. 3D).

従つて、上限下限切換回路105の出力には、
上限と下限のしきい値周波数信号が交互に出力さ
れる。また、フイルタ入力切換回路106へ供給
する切換信号#2は、トリガ信号が入力された後
高周波信号の有効な情報を含む時間区間と等しい
間は高周波信号を選択し、その後次のトリガ信号
が入力されるまでの間は上限下限切換回路105
の出力を選択するようにフイルタ入力切換回路1
06を制御する信号である(第3図ハ)。
Therefore, the output of the upper/lower limit switching circuit 105 is as follows:
Upper and lower threshold frequency signals are output alternately. In addition, the switching signal #2 supplied to the filter input switching circuit 106 selects the high frequency signal for a period equal to the time period including valid information of the high frequency signal after the trigger signal is input, and then the next trigger signal is input. The upper and lower limit switching circuit 105
Filter input switching circuit 1 to select the output of
06 (Figure 3C).

その結果、YIGフイルタへの入力信号は、高周
波信号の有効な情報を含む時間区間T1では高周
波信号が供給され、高周波信号の無効な情報を含
む時間区間T1又はT2では、上限と下限のしきい
値周波数信号がトリガ信号が入力される毎に交互
に供給された信号となる(第3図ホ)。
As a result, the input signal to the YIG filter is supplied with a high frequency signal in the time interval T 1 containing valid information of the high frequency signal, and with the upper and lower limits in the time interval T 1 or T 2 containing invalid information of the high frequency signal. The threshold frequency signal becomes a signal that is alternately supplied each time a trigger signal is input (FIG. 3(e)).

また、ビデオ回路7の出力ビデオ信号はバツフ
ア108を介して極性切換回路110の一方の入
力となり、また反転増幅器107で極性反転を受
けてバツフア109を介して極性切換回路110
の他方の入力となつている。
Further, the output video signal of the video circuit 7 becomes one input of the polarity switching circuit 110 via the buffer 108, and also undergoes polarity inversion in the inverting amplifier 107 and passes through the buffer 109 to the polarity switching circuit 110.
This is the other input.

極性切換回路110は前記切換信号#1を受け
てバツフア108、同109の両出力を交互に切
換えて積分入力切換回路111の一方の入力端へ
送出する。
The polarity switching circuit 110 receives the switching signal #1, alternately switches the outputs of the buffers 108 and 109, and sends the outputs to one input terminal of the integral input switching circuit 111.

積分入力切換回路111の他方の入力端には後
続する積分回路112の積分出力が入力されてい
る。この積分入力切換回路111は前記切換信号
#2を受けて両入力を交互に切換えて積分回路1
12へ送出する。
The integral output of the following integral circuit 112 is input to the other input terminal of the integral input switching circuit 111. This integral input switching circuit 111 receives the switching signal #2 and alternately switches both inputs to
12.

積分回路112は積分入力切換回路111の出
力を受けてこれを積分し加算器113の一方の入
力端へ送出する。加算器113の他方の入力端へ
は電圧選択回路4の出力が供給され、両入力値の
加算値を電圧−電流変換回路5へ送出する。
Integrating circuit 112 receives the output of integral input switching circuit 111, integrates it, and sends it to one input terminal of adder 113. The output of the voltage selection circuit 4 is supplied to the other input terminal of the adder 113, and the added value of both input values is sent to the voltage-current conversion circuit 5.

その結果、YIGフイルタ2の選別特性の周波数
分布が電圧−電流変換回路5の出力電流値に応じ
て決定される。YIGフイルタ2の周波数選別特性
の周波数分布は、電圧選別回路4が電圧V1を選
別した場合には分布31、電圧V2では分布32、
電圧V3では分布33となるが、加算器113の
出力値は電圧選別回路4が選別した電圧値に積分
回路112の出力積分値で修正されるので、YIG
フイルタ2の周波数選別特性が温度変化等により
ずれた場合に電圧−電流変換回路5に入力される
YIGフイルタ2の周波数選別特性を決める電圧が
補正される。
As a result, the frequency distribution of the selection characteristic of the YIG filter 2 is determined according to the output current value of the voltage-current conversion circuit 5. The frequency distribution of the frequency selection characteristic of the YIG filter 2 is distribution 31 when the voltage selection circuit 4 selects the voltage V 1 , distribution 32 for the voltage V 2 ,
For voltage V 3 , the distribution is 33, but since the output value of the adder 113 is corrected by the voltage value selected by the voltage selection circuit 4 by the output integral value of the integration circuit 112, YIG
When the frequency selection characteristic of the filter 2 deviates due to temperature change, etc., it is input to the voltage-current conversion circuit 5.
The voltage that determines the frequency selection characteristics of the YIG filter 2 is corrected.

次に、第4図および第5図を参照してYIGフイ
ルタ2の周波数選別特性が低い周波数側にずれた
場合の補正動作を説明する。
Next, with reference to FIGS. 4 and 5, a correction operation when the frequency selection characteristic of the YIG filter 2 deviates to the lower frequency side will be described.

まず、第4図において、YIGフイルタ2の周波
数選別特性の周波数分布は中心周波数がf1である
周波数分布31が選別されており、この周波数分
布31の中心周波数がf1からf1−fDにずれたとす
る(第4図イ)。
First, in FIG. 4, the frequency distribution of the frequency selection characteristic of the YIG filter 2 is such that a frequency distribution 31 whose center frequency is f 1 is selected, and the center frequency of this frequency distribution 31 is from f 1 to f 1 −f D (Figure 4 A).

高周波信号は第2図と同様であり、中心周波数
f1、同f2、同f3の高周波信号21、同22、同2
3が時間区間T1(第3図参照)においてYIGフイ
ルタ2へ入力する(第4図ロ)。
The high frequency signal is the same as in Figure 2, with the center frequency
High frequency signals 21, 22, 2 of f 1 , f 2 and f 3
3 is input to the YIG filter 2 in the time interval T 1 (see FIG. 3) (FIG. 4 b).

一方、上限下限切換回路105から上限のしき
い値周波数信号f1Mと下限のしきい値周波数信号
f1Lが夫々時間区間T2、同T3(第3図参照)にお
いてYIGフイルタ2へ入力する(第4図ハ,ニ)。
しかし、YIGフイルタ2の周波数分布31は低い
周波数側にずれたので、上下限のしきい値周波数
信号f1L、同f1Mの中、下限のしきい値周波数信号
f1LがYIGフイルタ2の周波数分布31内に入る
ことになる。また、この周波数分布31には高周
波信号21が入つている。
On the other hand, the upper limit threshold frequency signal f 1M and the lower limit threshold frequency signal from the upper limit/lower limit switching circuit 105
f 1L is input to the YIG filter 2 in time intervals T 2 and T 3 (see FIG. 3), respectively (FIG. 4 C and D).
However, since the frequency distribution 31 of the YIG filter 2 shifted to the lower frequency side, the upper and lower limit threshold frequency signals f 1L and the middle and lower limit threshold frequency signals f 1M
f 1L falls within the frequency distribution 31 of the YIG filter 2. Further, this frequency distribution 31 contains a high frequency signal 21.

その結果、YIGフイルタ2からは時間区間T1
において高周波信号21が、時間区間T3におい
てしきい値周波数信号f1Lが夫々出力されること
になる(第4図ホ,ヘ,ト)。
As a result, from YIG filter 2, time interval T 1
The high frequency signal 21 is output in the time interval T3 , and the threshold frequency signal f1L is output in the time interval T3 (FIG. 4, E, F, and G).

次に、第5図において、ビデオ回路7から検波
されて出力される信号は、時間区間T1にはYIG
フイルタ2によつて周波数選別された高周波信号
の検波信号となり、時間区間T2には無信号Ov
電圧)となり、時間区間T3には、下限のしきい
値周波数信号となる(第5図ロ)。
Next, in FIG. 5, the signal detected and output from the video circuit 7 is YIG in the time interval T1 .
It becomes a detection signal of the high frequency signal frequency-selected by the filter 2, becomes a no-signal O v voltage in time interval T 2 , and becomes a lower limit threshold frequency signal (5th voltage) in time interval T 3 . Figure b).

このビデオ回路7の検波信号はバツフア108
に入力され、バツフア108の出力は、極性切換
回路110に入力される(第5図ハ)。
The detection signal of this video circuit 7 is transmitted to the buffer 108.
The output of the buffer 108 is input to the polarity switching circuit 110 (FIG. 5C).

又、ビデオ回路7の検波信号は、反転増幅器1
07でその極性が反転されて負の電圧信号として
バツフア109へ入力され、バツフア109の出
力は極性切換回路110へ入力される(第5図
ニ)。極性切換回路110は、切換信号#1によ
つて上限下限切換回路105と同期して切換り、
上限下限切換回路105が上限の周波数しきい値
信号f1Mを選択した時は、バツフア109の出力
を選択し、上限下限切換回路105が下限の周波
数しきい値信号f1Lを選択した時はバツフア10
8の出力を選択し、積分入力切換回路111へ出
力する(第5図ホ)。
Furthermore, the detection signal of the video circuit 7 is transmitted to the inverting amplifier 1.
At step 07, the polarity is inverted and input as a negative voltage signal to the buffer 109, and the output of the buffer 109 is input to the polarity switching circuit 110 (FIG. 5D). The polarity switching circuit 110 switches in synchronization with the upper/lower limit switching circuit 105 by switching signal #1,
When the upper/lower limit switching circuit 105 selects the upper limit frequency threshold signal f 1M , the output of the buffer 109 is selected, and when the upper/lower limit switching circuit 105 selects the lower limit frequency threshold signal f 1L , the output of the buffer 109 is selected. 10
8 is selected and outputted to the integral input switching circuit 111 (FIG. 5, E).

積分入力切換回路111は、切換信号#2によ
つて、フイルタ入力切換回路106と同期して切
換わり、フイルタ入力切換回路106が高周波信
号を選択した時は積分回路112の出力を選択し
(時間区間T1)、フイルタ入力切換回路106が
上限下限切換回路105の出力を選択した時は、
極性切換回路110の出力を選択し(時間区間
T2、同T3)、積分回路112へ出力する(第5図
ヘ)。積分回路112は積分入力切換回路111
から入力される信号を時間積分し、加算器113
へ出力する(第5図ト)。
Integral input switching circuit 111 switches in synchronization with filter input switching circuit 106 by switching signal #2, and when filter input switching circuit 106 selects a high frequency signal, selects the output of integrating circuit 112 (time section T 1 ), when the filter input switching circuit 106 selects the output of the upper/lower limit switching circuit 105,
Select the output of the polarity switching circuit 110 (time interval
T 2 , T 3 ) and output to the integrating circuit 112 (FIG. 5). Integrating circuit 112 is integral input switching circuit 111
Adder 113
(Figure 5).

ここで、積分回路112へは時間区間T3にお
ける下限しきい値周波数信号f1Lに係る検波信号
が入力され、これが蓄積され所要の正の値として
加算器113へ入力される。
Here, the detection signal related to the lower limit threshold frequency signal f 1L in the time interval T 3 is input to the integrating circuit 112, which is accumulated and input to the adder 113 as a required positive value.

従つて、加算器113では、電圧選択回路4か
ら供給される電圧V1に、積分回路112から入
力される正の電圧が加算され、V1より大きい電
圧が電圧−電流変換回路5に供給されるので、
YIGフイルタ2に供給される電流も電圧−電流供
給回路5にV1が供給されていた時より増加し、
YIGフイルタ2の周波数選択特性を高い周波数へ
ずらすよう補正する。この補正は、YIGフイルタ
2の周波数選択特性の低い周波数側の遮断周波数
が下限のしきい値周波数f1Lより高くなるまで行
なわれる。また、周波数選択特性が高い周波数側
にずれ、上限のしきい値周波数信号の周波数f1M
がYIGフイルタ2の周波数選別特性の分布内に入
つた場合には時間区間T2に上限のしきい値周波
数信号の検波信号がビデオ回路7から出力され
る。この信号は反転増幅器107で反転されて、
負の電圧信号となりバツフア109に入力され
る。極性切換回路110は時間区間T2にはバツ
フア109の出力を選択して、積分入力切換回路
に出力するので、上限のしきい値周波数信号の検
波信号は積分入力切換回路111に供給され、積
分入力切換回路111の出力は積分回路112に
入力され時間積分されて加算器113に入力され
る。従つて、加算器113で電圧V1に加算され
る電圧は負の電圧となるため、YIGフイルタ2の
周波数選択特性を低い周波数へずらすよう補正す
る。この補正はYIGフイルタ2の周波数選択特性
の高い周波数側の遮断周波数が上限のしきい値周
波数f1Mより低くなるまで行なわれる。
Therefore, in the adder 113, the positive voltage inputted from the integrating circuit 112 is added to the voltage V1 supplied from the voltage selection circuit 4, and a voltage larger than V1 is supplied to the voltage-current conversion circuit 5. Because
The current supplied to the YIG filter 2 also increases compared to when V 1 was supplied to the voltage-current supply circuit 5,
Correct the frequency selection characteristic of YIG filter 2 to shift it to a higher frequency. This correction is performed until the cut-off frequency on the lower frequency side of the frequency selection characteristic of the YIG filter 2 becomes higher than the lower limit threshold frequency f 1L . In addition, the frequency selection characteristic shifts to the higher frequency side, and the frequency of the upper threshold frequency signal f 1M
falls within the distribution of the frequency selection characteristic of the YIG filter 2, a detected signal of the upper threshold frequency signal is output from the video circuit 7 in the time interval T2 . This signal is inverted by an inverting amplifier 107 and
This becomes a negative voltage signal and is input to the buffer 109. The polarity switching circuit 110 selects the output of the buffer 109 during time interval T2 and outputs it to the integral input switching circuit, so the detection signal of the upper threshold frequency signal is supplied to the integral input switching circuit 111, The output of the input switching circuit 111 is input to an integrating circuit 112, time-integrated, and input to an adder 113. Therefore, since the voltage added to the voltage V 1 by the adder 113 becomes a negative voltage, the frequency selection characteristic of the YIG filter 2 is corrected to shift to a lower frequency. This correction is performed until the cutoff frequency on the higher frequency side of the frequency selection characteristic of the YIG filter 2 becomes lower than the upper limit threshold frequency f 1M .

以上のように、YIGフイルタ2の周波数選別特
性の温度変化によるずれを補正することができ
る。なお、上記実施例ではしきい値周波数信号発
生回路が発生する複数対のしきい値周波数信号を
しきい値周波数選択回路で選択して上限下限切換
回路へ出力するようにしたが、しきい値周波数選
択回路を省略して直接上限下限切換回路で選択出
力するようにしても良い。
As described above, deviations in the frequency selection characteristics of the YIG filter 2 due to temperature changes can be corrected. In the above embodiment, the threshold frequency selection circuit selects a plurality of pairs of threshold frequency signals generated by the threshold frequency signal generation circuit and outputs them to the upper/lower limit switching circuit. The frequency selection circuit may be omitted and the upper/lower limit switching circuit may directly select and output the frequency.

(発明の効果) 以上詳述したように、本発明のYIGフイルタの
駆動回路によれば、YIGフイルタの周波数選別特
性の周波数分布を挟む両側にしきい値周波数信号
を設け、周波数選択特性の周波数分布が温度の影
響で低域周波数側又は高域周波数側のいずれの方
向へずれた場合でも、上限又は下限のしきい値周
波数信号のいずれか一方が周波数選択特性の周波
数分布に入るようにし、この周波数分布に入つた
しきい値周波数信号の積分値でもつてYIGフイル
タの駆動電流を補正するようにしたので、温度変
化によつてYIGフイルタおよびその駆動回路に変
動があつてYIGフイルタの周波数選択特性の周波
数分布が正規の位置からずれた場合、これを自動
的に補正することができる。
(Effects of the Invention) As described in detail above, according to the YIG filter drive circuit of the present invention, threshold frequency signals are provided on both sides of the frequency distribution of the frequency selection characteristic of the YIG filter, and the frequency distribution of the frequency selection characteristic is Even if the frequency shifts toward either the lower frequency side or the higher frequency side due to the influence of temperature, either the upper or lower threshold frequency signal will fall into the frequency distribution of the frequency selection characteristic, and this Since the drive current of the YIG filter is corrected using the integral value of the threshold frequency signal that has entered the frequency distribution, the YIG filter and its drive circuit will fluctuate due to temperature changes, which will affect the frequency selection characteristics of the YIG filter. If the frequency distribution of deviates from the normal position, this can be automatically corrected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係るYIGフイルタ
の駆動回路のブロツク図、第2図は本発明に係る
しきい値周波数信号とYIGフイルタの周波数選択
特性の周波数との関係を示す説明図、第3図は
YIGフイルタへの入力信号のタイミング図、第4
図はYIGフイルタの周波数選別特性が低い周波数
側にずれた場合のYIGフイルタの出力信号の周波
数分布図、第5図は積分回路の入出力のタイミン
グ図、第6図は従来のYIGフイルタの駆動回路の
ブロツク図、第7図は従来のYIGフイルタの駆動
回路の動作を示す周波数分布図、第8図は従来の
問題点の説明図で、温度の影響によつてYIGフイ
ルタの周波数選別特性が高い周波数側にずれた場
合のYIGフイルタの出力信号の周波数分布図であ
る。 1…高周波信号入力端子、2…YIGフイルタ、
3…電圧発生回路、4…電圧選択回路、5…電圧
−電流変換回路、6…中間周波回路、7…ビデオ
回路、8…ビデオ信号出力端子、101…トリガ
信号入力端子、102…制御回路、103…しき
い値周波数信号発生回路、104…しきい値周波
数信号選択回路、105…上限下限切換回路、1
06…フイルタ入力切換回路、107…反転増幅
器、108,109…バツフア、110…極性切
換回路、111…積分入力切換回路、112…積
分回路、113…加算器。
FIG. 1 is a block diagram of a YIG filter drive circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the relationship between the threshold frequency signal and the frequency of the frequency selection characteristic of the YIG filter according to the present invention. , Figure 3 is
Timing diagram of input signal to YIG filter, 4th
The figure is a frequency distribution diagram of the output signal of the YIG filter when the frequency selection characteristic of the YIG filter shifts to the lower frequency side, Figure 5 is the input/output timing diagram of the integrating circuit, and Figure 6 is the drive of the conventional YIG filter. The circuit block diagram, Fig. 7 is a frequency distribution diagram showing the operation of the conventional YIG filter drive circuit, and Fig. 8 is an explanatory diagram of the problems with the conventional method. FIG. 4 is a frequency distribution diagram of the output signal of the YIG filter when the frequency is shifted to the higher frequency side. 1...High frequency signal input terminal, 2...YIG filter,
3... Voltage generation circuit, 4... Voltage selection circuit, 5... Voltage-current conversion circuit, 6... Intermediate frequency circuit, 7... Video circuit, 8... Video signal output terminal, 101... Trigger signal input terminal, 102... Control circuit, 103...Threshold frequency signal generation circuit, 104...Threshold frequency signal selection circuit, 105...Upper/lower limit switching circuit, 1
06... Filter input switching circuit, 107... Inverting amplifier, 108, 109... Buffer, 110... Polarity switching circuit, 111... Integral input switching circuit, 112... Integrating circuit, 113... Adder.

Claims (1)

【特許請求の範囲】[Claims] 1 YIGフイルタに所要値電流を供給しその周波
数選択特性の周波数分布を設定するYIGフイルタ
の駆動回路であつて、前記YIGフイルタの前記周
波数分布の高域遮断周波数および低域遮断周波数
に近接し、かつ該周波数分布の外側に適宜周波数
だけ離隔した周波数の信号である上限しきい値周
波数信号および下限しきい値周波数信号を発生す
るしきい値周波数信号発生器と;前記上限しきい
値周波数信号と下限しきい値周波数信号を受けて
両者を交互に切り換えて出力する上限下限切換回
路と;一定の繰返し周波数で繰り返され所定周波
数分布を有する高周波信号を一方の入力とし、前
記上限下限切換回路の出力を他方の入力とし、両
入力を交互に切換えて前記YIGフイルタに出力す
るものであつて、高周波信号の前記繰返し周期内
の所定の一部時間において他方の入力を選択する
フイルタ入力切換回路と;前記YIGフイルタの出
力を受けてそれをビデオ信号に変換するビデオ回
路と;前記ビデオ信号を受けてそれを反転増幅す
る反転増幅器と;前記上限下限切換回路の切換動
作に同期して前記反転増幅器の出力と前記ビデオ
回路の出力を交互に切り換えて出力する極性切換
回路と;所要の積分動作を行なう積分回路と;前
記フイルタ切換回路の切換動作に同期して前記積
分回路の出力と前記極性切換回路の出力とを交互
に切り換えて前記積分回路へ出力する積分入力切
換回路と;前記YIGフイルタの周波数選択特性を
規定すべく所要値の電圧を発生する電圧発生回路
と;前記電圧発生回路が発生する電圧と前記積分
回路の出力とを受けて両入力値を加算した所要値
電圧を出力する加算器と;前記加算器の出力電圧
を受けて前記YIGフイルタへ前記所要値電流の供
給を行なう電圧−電流変換回路と;を備えている
ことを特徴とするYIGフイルタの駆動回路。
1 A drive circuit for a YIG filter that supplies a required value of current to the YIG filter and sets the frequency distribution of its frequency selection characteristic, which is close to the high cutoff frequency and the low cutoff frequency of the frequency distribution of the YIG filter, and a threshold frequency signal generator that generates an upper threshold frequency signal and a lower threshold frequency signal that are signals of frequencies separated by an appropriate frequency outside the frequency distribution; an upper and lower limit switching circuit that receives a lower limit threshold frequency signal and alternately switches between the two and outputs the same; one input is a high frequency signal that is repeated at a constant repetition frequency and has a predetermined frequency distribution, and the output of the upper and lower limit switching circuit; as the other input, and which alternately switches both inputs and outputs them to the YIG filter, and selects the other input at a predetermined part of time within the repetition period of the high frequency signal; a video circuit that receives the output of the YIG filter and converts it into a video signal; an inverting amplifier that receives the video signal and inverts and amplifies it; and an inverting amplifier that receives the output of the YIG filter and inverts and amplifies it; a polarity switching circuit that alternately switches and outputs the output and the output of the video circuit; an integrating circuit that performs a required integral operation; an output of the integrating circuit and the polarity switching circuit in synchronization with the switching operation of the filter switching circuit; an integral input switching circuit that alternately switches the output of the YIG filter and outputs it to the integrating circuit; a voltage generating circuit that generates a voltage of a required value to define the frequency selection characteristics of the YIG filter; an adder that receives the voltage and the output of the integrating circuit and outputs a required value voltage obtained by adding both input values; a voltage that receives the output voltage of the adder and supplies the required value current to the YIG filter; A YIG filter drive circuit comprising: a current conversion circuit;
JP28978585A 1985-12-23 1985-12-23 Driving circuit for yig filter Granted JPS62147875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28978585A JPS62147875A (en) 1985-12-23 1985-12-23 Driving circuit for yig filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28978585A JPS62147875A (en) 1985-12-23 1985-12-23 Driving circuit for yig filter

Publications (2)

Publication Number Publication Date
JPS62147875A JPS62147875A (en) 1987-07-01
JPH0458754B2 true JPH0458754B2 (en) 1992-09-18

Family

ID=17747737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28978585A Granted JPS62147875A (en) 1985-12-23 1985-12-23 Driving circuit for yig filter

Country Status (1)

Country Link
JP (1) JPS62147875A (en)

Also Published As

Publication number Publication date
JPS62147875A (en) 1987-07-01

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